Algorithmic Design of Digital Operational Units with Low Power Consumption

 
Audzeyeu M.A., Bibilo P.N. (United Institute of Informatics Problems)
 
Abstract - The lowering of power consumption in CMOS VLSI digital systems is one of the most important problems that appear now before developers of CAD systems [1 3]. One of the effective approaches to lowering the dynamic power consumption is creation of an algorithmic description of the VHDL project, which provides for the deactivation of some functional blocks which are not necessary in particular moments. Contemporary synthesizers fulfill the high level synthesis of logic circuits by substitution of description of each VHDL construction with functionally structural description of a proper logic subcircuit. The results of digital logic circuit synthesis (the number of logic elements and power consumption) depend significantly on initial VHDL code [4]. During initial VHDL code development it is possible to use different approaches to improve some parameters of synthesized logic circuit. At the algorithmic level of the digital design, it is necessary to provide for disconnection of the units, which cause the higher power consumption [5]. In this paper such methods of algorithmic VHDL description of logic circuit are studied. The efficiency of the proposed methods is compared with the traditional method of VHDL-description which does not take into account the aspect of power consumption [6, 7] and is oriented only to the correct functionality of the developed logic circuit. To estimate the power consumption of logic circuits the approach [5] is used which allows applying high-speed logical VHDL-simulation of structural descriptions (netlists) of logic circuits instead of slow SPICE simulation. The main conclusion of the provided study is the following. The clock gating [8, 9] and the storage of operand values for complex operations as well as zero value setting for simple ones are effective methods for the VHDL description [10-13] of operational units with low power consumption implemented in the CMOS basis.

Keywords - digital design, digital logic synthesis, digital logic simulation, power consumption, VHDL, VLSI, CMOS.

Алгоритмическое проектирование цифровых операционных устройств с пониженным энергопотреблением

 
Авдеев Н.А., Бибило П.Н. (Объединенный институт проблем информатики НАН Белоруссии, г. Минск)
 
Аннотация - Предлагаются способы описания на языке VHDL синтезируемых моделей цифровых операционных устройств, состоящих из управляющего и операционного автоматов. После выполнения синтеза логических схем в библиотеке проектирования заказных цифровых КМОП СБИС и моделирования результаты сравниваются по площади и энергопотреблению полученных схем. Существенного снижения энергопотребления логических схем можно добиться, используя соответствующее описание функционирования цифровых устройств на алгоритмическом уровне.

Ключевые слова - операционное цифровое устройство, синтез логической схемы, моделирование,VHDL, СБИС, КМОП-технология.