Means of Automating the Hierarchical Design of Complex Microelectronic Circuits with Uncertainty of Design Rules

 
Mironov S.E., Vasiliyev A.Yu. (Saint Petersburg Electrotechnical University "LETI"), Safyannikov N.M. (Saint Petersburg Electrotechnical University "LETI", )
 
Abstract - Complication of microelectronic circuits and systems has led to the development of means for automating the design of the layout of complex objects with the uncertainty of design rules, which allow to quickly adapt topology to the technological requirements of the manufacturer. These design tools are called layout compaction systems, since the adjustment to the required design rules is performed by “compacting” the elements of layout placed in the abstract flat space to each other. This article describes software and methods for developing VLSI macroblocks, created by authors for high density design in conditions of uncertainty of project standards. The technological invariance of projects of the VLSI macroblocks layout is achieved with the help of the layout compaction system “TopDesign”, minimizing the distance between the elements in accordance with the design rules and the restrictions imposed by the developer on the location of individual parts of the layout. The high packing density of the layout of hierarchical VLSI blocks is provided by the original method, of iterative step-by-step matching of the cell dimensions and the position of their terminals. Aspects of compaction associated with the agreement of the dimensions and positions of the cell deductions were considered in the works of the authors. There it was also discussed the assembly of cells from complex microelectronic circuits — VLSI macroblock. This article describes the structural model proposed by the authors of the layout of complex hierarchical irregular schemes, which simplifies the matching of their cells. The description of the developed system “Matching of Cells” and methods of hierarchical design of layout of complex microelectronic circuits with its help is given. The described method of hierarchical layout design with the help of the “Matching of Cells” system was successfully applied within the framework of the state task of the Ministry of Education and Science of the Russian Federation № 8.2080.2017/4.6 when carrying out works that continue to investigate the authors of designing microelectronic circuits as small, and of great complexity.

Keywords - automation of design; microelectronic circuits; VLSI CAD; uncertainty of design rules; layout compaction

Средства автоматизации иерархического проектирования сложных микроэлектронных схем при неопределенности проектных норм

 
Миронов С.Э., Васильев А.Ю. (Санкт-Петербургский государственный электротехнический университет, г. Санкт-Петербург), Сафьянников Н.М. (Санкт-Петербургский государственный электротехнический университет, ООО "ЛЭТИНТЕХ", г. Санкт-Петербург)
 
Аннотация - Приводятся результаты исследований авторов по технологически инвариантному проектированию топологии сложных иерархических микроэлектронных схем. Описывается предложенная авторами структурная модель топологии сложных нерегулярных схем, которая упрощает согласование их ячеек. Приводятся описание разработанной системы “Matching of Cells” и методики иерархического проектирования топологии сложных микроэлектронных схем с ее помощью.

Ключевые слова - автоматизация проектирования топологии; иерархические микроэлектронные схемы; САПР СБИС; технологически инвариантное проектирование; сжатие топологии.