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Listing of works with the partition by the subject of reports. Click on the work title to see its details. The selected set may be restricted by specifying a range of conference years, or by selecting a specific topic.

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ADC design problems
Cellular automata
Design of System-on-chip (SoC) and IP-blocks
Design of VLSI elements
Design of VLSI signal processors
Design of analog and mixed functional blocks of VLSI
Design of digital functional blocks of VLSI
Design of fault-tolerance systems
Design of micro-electromechanical systems
Design of nanoelectronic devices
Design of nanoelectronic devices based on Josephson junctions
Design of photodetecting VLSI
Design of radiation-resistant VLSI
Design of technological processes
Designing components for aerospace and navigation technology
Genetic algorithms in VLSI CAD
Methods and algorithms for automated layout design
Methods for high-level simulation
Methods of device technology simulation of VLSI
Methods of digital information processing and digital filters
Methods of electro-thermal simulation
Methods of logic synthesis and functional logic simulation ...
Methods of simulation of VLSI electrical characteristics
Models of devices for circuit simulation
Problems of development of sensory microcircuitry
Simulation of data transfer channels
Study of the magnetic properties of materials
Unconventional computing systems
design of memory cells
Selected papers: from 2005 to 2018 year
In selection - 941 papers
A 1W, 800 MHz RF Monolithic Integrated Circuit Power Amplifier Based on Silicon Technology
A 2-bit Flash ADC for Pipeline Circuits
A 4-channel Multi-standard Adaptive Serial Transceiver for the Range 1.25-10.3Gb/s in CMOS 65nm
A 8-bit flash ADC with reduced DNL
A 14-bit 100 MS/s Pipelined ADC
ADC for radiation-proof IP blocks
A Fast Algorithm for Finding Vertices Accessible via Constrained Paths in a Control Flow Graph
A Hardware and Software Complex of Experimental Tryout for Radioelectronic Facility Signal Simulation, Registration and Analysis
A High Speed ADC with Low Power Consumption
A High Speed Level Shifter for High Voltage Supply Range with High Reliability
A Library of Self-Timed Elements or ASIC-Technology
AMS components design for System in Package
A Method for Scalable Verification of PROMELA Models of Cache Coherence Protocols
A Method of Functional Test Generation for HDL Descriptions Based on Model Checking of High-Level Decision Diagrams
A Method of Multi-level Uniform Grids for Spatial Searching
A New Approach in Design of IIR Digital Filters
A Parasitic Resistance Extraction Method for Early Analysis of Complex Shaped Power Delivery Networks
A Pipelined Analog-to Digital Converters With Digital Calibration
A Practical Approach to Verification of Multicore Microprocessor Models
A Precision Voltage-to-Frequency Converter Design
ASIAN - Self-Timed Logic Circuits Analysis Subsystem
ASPECT – a Subsystem of Event Analysis of Self-Timed Circuits
About duplication of elements at VLSI layout
About the Possibility of Chaotic Oscillations of Charge on Ferroelectric Capacitor with Negative Differential Capacity in Oscillatory Circuit with Fractal Input Voltage
Accuracy Estimation of Discrete Optimization Algorithms
Accuracy Improvement of the Interconnect Parasitic Capacitance Extraction
Accuracy and adequacy of the analytical modeling of the temperature distribution in thermal microsystems
Accurate High-speed Frequency Meter for Doppler Initial Velocity Measurement
Adaptation in Problems of VLSI Topology Designing
Adaptation of performance tests for the 64-bit universal superscalar microprocessor
Adaptive Antenna Array in Real-Valued Arithmetic
Adaptive arrays for digital communication systems: problems and solutions
Adaptive method of harmonic balance
Adaptive procedure of choice of modules orientation at VLSI planning
Adjustable error-correcting encoder for Systems on Chip
Adoption of Genetic Algorithms for running in elastic compute environment concerning CAD applications
Advantages of Dataflow Computing Model
A fast algorithm for data dependency tracking in Software and Firmware analysis and testing
A global router for nanometer standard cells
A graphical dataflow meta-language for asynchronous distributed programming
Alarm controllers MS-0226 and ÌÑ-0226G on the basis of platform "MULTICORE"
Algebraic Decomposition Models for Digital System Design Debugging by Simulation
Algorithm for Constructing Voronoi Diagram of Orthogonal Polygons in Linf-metric
Algorithm for design rule violation clean-up after physical design
Algorithmic Design of Digital Operational Units with Low Power Consumption
Algorithm of Inter-gate Resynthesis at the Transistor Level for Computer-aided Design of Microelectronic Circuits
Algorithm of Synthesizing Radar Scene Images in Passive SAR being the Part of Airborne Bi-static Radar System of General Configuration
Algorithm of assigning operations for specialized processors with clusterized resources
Algorithms for Functional Correction of Boolean Circuits
Algorithms for adaptive filtering of nonstationary signal based on parallel computations
Algorithms for dynamic all-pairs shortest path problem
Algorithms of evolutionary swarm intelligence for solving graph partition problem
Algorithms of the parallel computations in the formalization of cellular automata: the sorting of strings and the multiplication of numbers by Atrubin’s method
A method for reducing timing delay temperature dependence of digital integrated circuits
Amorphous glass-coated microwires for applications as embedded stress sensors in functional materials
An 8-bit segmented DAC with high conversion rate
An Algorithm for determining the size of transistors, based on statistical static timing analysis
An Efficient Router Bufferization for Network-on-Chip Design
An adaptive random search algorithm for parametric identification of electronic components’ models
Analog-digital "system-on-chip" MF01 of series "Multiflex"
Analog-digital "system on crystal" peripheral controller MCT-01 on the basis of IP-libraries of a platform "MULTICORE"
Analog-digital VLSI of a high-speed frequency synthesizer on SiGe BiCMOS 0,25 mkm technology
Analog-digital interfaces of the mixed systems on a crystal
Analog-digital microcircuits on the basis of Si-Ge technology – a new direction in a domestic SHF systems engineering
Analog and digital micro- and nanoelectronics circuits for communications
Analogous voltage multipliers based on bipolar transistors and MOSFET
Analog simulation tools and their role in modern designing integrated circuits
Analysis Based on TCAD Simulation of Failure Tolerance of the Elements on the Cells STG DICE for 65-nm CMOS Blocks of Associative Memory
Analysis and synthesis of arithmetic unit of a field of Galois of prof. Pospelov D.A.
Analysis of Distortions Caused by Impulses in Switching Transistors Sources in Current-Steering DAC
Analysis of Distortions Caused by Output Capacitance Modulation in Current-Steering DAC
Analysis of Power Consumption of Matching Signals Summation Circuits for 65 nm CMOS Associative Memory Registers
Analysis of efficiency of complex use low-power techniques for blocks of digital VLSI
Analysis of modern microprocessors peak performance
Analysis of optimization process of analog circuits on the basis of Lyapunov function
Analysis of problems of digital filtering and way of their solution
Analysis of the Lyapunov function of the process of designing analog circuits
Analysis of the effect of accelerating the optimization of electronic circuits
Analysis of the effect of membrane shape at mechanical strength and parameter stability of MEMS pressure sensors
Analysis of the impact of standard cells placement and power network configuration on the layout design of a microprocessor component
Analytical Timing Driven Global Placement of Structured ASIC
An approach to hardware test point insertion automation based on hardware reengineering tools
Ant algorithm for determining the critical linkages in VLSI
A parallel critical path algorithm with loop detection for static timing analysis of sequential circuits
A physical synthesis to islands of cells with the same diffusion width
Application of Selective Techniques for Parametric Model Order Reduction
Application of a technique of not destroying control of dose stability of parties SoS CMOS VLSI
Application of autophotoelectronic semiconductor microstructures for the analysis of gas mixes
Application of dynamic Voronoy diagrams to design rule checking
Application of grid representations for compression of graphical information
Application of packages of plate support as the tool of adaptation of specialized operational systems for functioning on platform "MULTICORE"
Application of quasi-hydrodynamic model for the analysis of electronic transport in field and bipolar transistors in conditions of a pulse ionizing radiation in view of the raised temperatures
Application of spectrum sensing technique for the design of radio receivers of spectrally sparse signals
Application of standard cell characterization results in statistical timing analysis
Application of the maximum principle of Pontryagin for a problem of circuit optimization
Application of the principles of adaptive filtering signals to the synthesis of invariant control systems unknown dynamic plants
Applying OpenCL Technology to Vector Processor Design
Appraisal of constructive-technological capabilities improvement of radiation hardening deep sub-micron VLSI
Approximation of the central Chi-square distributions for on-line computation of the false alarm probability for energy detector
Architectural features of VELCore-01 video processing core
Architecture and circuit design of precision differential amplifiers with high common mode rejection ratio
Architecture of DSP-accelerators on the basis of a platform "MultiCore" for supercomputers of new generation
Architecture of differential operational amplifiers with increased common-mode noise stability
Architecture of domestic IC series of type "system or network on chip" on the basis of IP-libraries of platform "MULTICORE"
Architecture of fault-resistant FPGA with capacity over 100 thousand gates
Architecture of the microwave differential operating amplifiers with paraphase output
Architecture of the unified computing block for contactless photon system of measurement of parameters of a rail track
Architecture validation tests for RTL-model of 64-bit superscalar microprocessor
Arithmetical algorithms of the coding system of 1 from 4 with an active zero and estimation of the parameters of high-speed performance and occupied area of the unit of summation
Assessment of Functional Stability of the Dynamic Sensor Network
A stick-diagram based standard cell layout synthesis tool
A technique to the design-for-testability automation of analogue IC based on OBIST
Automated Picosecond Laser Facility for Single Event Effects Simulation in Microelectronic Devices under Space Environment
Automated design of Networks-on-Chip with custom topology
Automatic Determining of Auxiliary Constraints at Boundaries for Standard Cells Synthesis Flow
Automatic layout synthesis of standard cell layouts based on re-using existing transistor placement patterns and routing patterns
Automatic tuning of digital polynomial regulators with help of artificial neural network
Automation of synthesis of VHDL-AMS models for the mixed and analog behavioural simulation
Automation of verification environments development process providing a through design flow for design, verification and research of IP-blocks and SoC
Autonomous parameters of of transistors of uncommited logic array ABMK_1_3 in radiation and temperature influences
Bases of circuit designing of active filters of HF and SHF ranges
Base ternary logic element on the basis of standard CMOS-technology
Bioinspired VLSI chip planning methods
Bioinspired VLSI chip planning methods
Biquad digital filters with non-canonical z-plane topography of poles
Bit error rate calculation in high performance communication channels
Block of Fast Fourier Transformation for wireless communication systems on the basis of
Block of decoder Viterbi for wireless communication systems on the basis of standard IEEE 802.16
Branches in the Dataflow Metalanguage UPL (METAL) and Methods of their Implementation in the PDCS “Buran”
Broadband integrated SHF doubler of frequency
Buffer stage of operational amplifiers with low output impedance and option rail-to-rail
Built-in self-repair for SRAM with redundant elements
“Cycle-To-Cycle” methodology for timing analysis of high speed synchronous interfaces
CAD system for self-timed electronic circuits RONIS
CAVLC encoder IP-core for H.264/AVC
CMOS-APS element with high charge-collection efficiency
CMOS 65-nm static RAM on DICE cells with spacing groups of transistors
CMOS analog blocks technology migration
CMOS circuit interval static timing analysis accounting for logic correlations
CMOS frequency divider by 2 with high stability of output signal duty cycle
Calculation 2D inductance for extraction problems
Calculation of inductance in problems of designing superconductive microelectronic structures
Calibration of numerical TCAD model for 180 nm SOI MOSFETs
Carbon nanostructures plasma-catalytic growth technology: features and field emission circuits’ application
Cellular Automata Computational Parallelism of Elementary Matrix Operations
Cellular automata methods of the numerical solution of mathematical physics equations for the hexagonal grid
Ceramics-based device of touch and contactless information input for avionics
Characteristics of the "Multicore" series controllers for FFT processing signal in real time and their application in radar
Characterization of Analog Circuits Based on Cloud Computing
Characterization of pseudodynamic elements
Choice of optimum connections in a tree in view of Elmore delays
Circuit Design of Synchronizing Devices Within High-speed Data Services
Circuit design methods of increasing the reliability of operational amplifiers with maximum speed in high-signal mode
Circuit design of UHF operational amplifiers for analog interfaces with strong negative feedback
Circuit design of the superconducting integrated converter frequency-voltage for the Voltage standard based on the Josephson junctions arrays
Circuit of the Functional Control for Combinational Circuits Based on R-code
Circuitry design features of radiation-resistant IC ABMC
Clock Tree Synthesis Optimization
Cognitive Contradiction’s Visualization for VLSI Layout Decomposition for Double Patterning Issues
Combinatorial Test Program Generation for Microprocessors Based on Formal Specifications of Instruction Set Architecture
Combined method of calculation of parasitic elements of substrate of integrated circuits
Common approaches to the FPU verification
Communication fabric IP-core for a system-on-chip
Comparative analysis of active mm-wave SiGe mixers
Comparative analysis of different hardware decoder architectures for IEEE 802.11ad LDPC code
Comparative analysis of different strategies of optimization of analog circuits
Comparative analysis of efficiency of different variants of the dynamic programming method for solving the problem of optimal placing of elements on the chip
Comparative analysis of the memory elements and sense amplifiers for high-temperature VLSI RAM
Comparison of Double-gate Junctionless and Traditional MOSFETs by Means of TCAD
Compensation method of voltage references second order component temperature drift
Compensation of parasitic capacitances of the active elements in electronic devices
Complex algorithm of switch box routing
Complex arithmetic coprocessor
Complex platform of functional verification of Mentor Graphics
Computational method for determining phase noise in oscillators
Computer-aided design of topology of functional blocks of custom digital VLSI
Computer memory subsystem optimization by providing guaranteed memory bandwidth
Computer simulation of MEMS components
Conditional jump re-alternation Limiting based speed-up of Directed Automated program testing
Configurable IP-cores architecture analysys using criterion of implementation ability in “MULTICORE” platform IP-library
Configuration of microelectronic means on the basis of iterative clusterization taking into account time delays
Constraint Driven VLSI Floorplanning by Non-Linear Optimization
Construction of systems of raised reliability based on residual arithmetics with application of modern methods and tools of designing
Constructive and technological design of silicon color photocells with deep color separation based on isotype ð+-ð junctions
Controller IP-block for control functions realization in SoC
Converting VLSI macroblock structure by regrouping uniform function blocks
Counterfeit IC detection based on s-parameters measurements
Creation of "system-on-chip" on the basis of PLIC with use of synthesized processor kernels
Creation of CAD - systems’ ontology using Protege 4.2
Criteria of a choice of models at calculation of device characteristics of submicronic transistor structures
Criteria of resolution of phase ambiguities for complexed multi-antenna global navigation satellite system
Cross-section Partitioning Technique for Multiple Cell Upsets Rate Simulation in Space Environment
DAC capacity optimization for OFDMA modulation
DFM Improvement of Hierarchical Layouts
Debugging and testing of VLSI models with use of the prototypes realized on PLIC
Debugging of the block of transformation of addresses of the microprocessor
Decision-feedback equalizer with active inductor for high-speed receiver
Decompilation of Flat CMOS Circuits in SPICE Format
Decomposition Algorithm of the Electronic Circuits with Elements with Varied Area
Decomposition and Minimization of Binary Decision Diagrams for Systems of Specified Boolean Functions
Decomposition of Boolean Functions for BDD
Decomposition on the basis of universal systems of functions and its application at logic and topological VLSI synthesis
Definition of competence areas of synthesis algorithms of combinational logic circuits
Delay-Insensitive Floating Point Multiply-Add-Subtract Unit
Delay Insensitive Circuits for Low Power and Highly Reliable Microprocessors
Delay noise analysis, using graph of constraint pairs
Delta-Sigma Modulator with 10 MHz Clock Frequency in 180 nm CMOS Technology
Dependence of MCU Sensitivity in SRAM on Data Pattern and angle of incident
Design Principles and Numerical Simulation of Microthermomechanical IR Imagers with Optical Readout
Design a functional model of FPGA whith single-driver technology in Xilinx ISE system
Design and Testing of Integrated Circuit for Micromechanical Accelerometer
Design and development of SOI CMOS OA
Design and development of monolithic IC of microwave GaN phase shifters
Design criteria of Frequency selection for the internal oscillator UHF RFID tags
Design features of the multipliers on the module using advanced CAD
Designing PLL-blocks for systems of synchronization of integrated devices of information processing
Designing SoC on the basis of library of IP-blocks GRLIB of company Gaisler Research
Designing and production problems of smart sensors controllers
Designing and simulation of the differential capacitive MEMS accelerometer main parameters
Designing of CMOS linear and matrix transformers of the X-ray image with the active sensor cells
Designing of SCIC of the multiloop DC-SQUID for superconducting multichannel magnetometric and gradientmetric systems
Designing of analogue circuits as a controllable dynamic process
Designing of a universal analog kernel of sigma-delta ADC of a sound range
Designing of custom-made blocks taking into account extraction RC parasitic parameters
Designing of regular circuits with consecutive connections of transistors
Designing on FPGA and SoC high-performance binary comparators of a big dimensionality
Designing on FPGA of high-speed finite state machines
Design method of DSP-oriented modular logarithmic forward converter
Design of IC package with ceramic substrate for multicore processor
Design of Power Efficient 14-port Register File and Translation Lookaside Buffer in 28-nm Process
Design of Self-Timed Circuits: a Functional Approach
Design of Voltage Comparators Based on the Elements of the Radiation-Hardened Low-Temperature BiJFET Array Chip MH2XA030
Design of basic blocks for millimeter wave receiver in CMOS 90 nm
Design of behavioral model of sample and hold circuit based on the results of chip testing
Design of digital CMOS circuits for extreme temperatures
Design of technology process of silicon-germanium heterobipolar transistors manufacture
Design of the error-correcting code blocks using the two-phase CMOS logic elements
Design of the hybrid CAM register
Design tools of high-performance dataflow computing systems
Detector of Free Parts of Radio Frequency Spectrum
Determination and comparison of M-factor for devices with the type defined by the user (GENERIC)
Development Principles of Debugging Tools for Recurrent-Computing Device
Development and Investigation of Algorithm of Sparse Matrices Multiplication Task for the Parallel Dataflow Computing System "Buran"
Development and designing of integrated thermoelements
Development and modeling for submicron PDCFET transistors
Development and researches of modern linear photosensitive devices with CCD
Development monolitic integrated SiGe HBT reciver for 57-64 GHz application
Development of Capsule Programming Means for Recurrent Data-flow Architecture
Development of FPGA Project for Microprocessor Prototype Module
Development of Hybrid Sensory Multiscomplex Construction with Elements of Radio Frequency Identification
Development of Methods for Architecturally-oriented Resynthesis in the Computer-aided Design Flow for FPGAs
Development of Methods for Genetic Synthesis of Fault-Tolerant Logic circuits
Development of Real Number Models of Analog IP Blocks for Mixed Signal SoC Verification
Development of Resynthesis Flow for Improving Logical Masking Features of Combinational Circuits
Development of Routing Algorithms in Networks on Chip with a Multiplicative Circulant Topology
Development of algorithm of three-dimensional layout of VLSI on the basis of iterative clusterization
Development of a monolithic IC receiver with a phase shifting is performed in the LO part
Development of an optimum design of a magnetic field sensor on the basis of lateral magnetic transistor using tools of device technological simulation
Development of behavioural cycle-accurate model of a system-on-chip with C++
Development of fabric density measurement system on the basis of the digital filter
Development of integral digital filters for sigma-delta converters using MATLAB
Development of manufacturing techniques of SoI plates
Development of methods for the analysis of defects in the gate dielectric on the test structures in the wafers
Development of microwave phase shifter based on SOI 0.18-micron technology
Development of precision digital-to-analog PLL devices and tools of their computer simulation
Development of specialized VLSI of type "system-on-chip" for digital two-system navigating receiver GLONASS/GPS
Development of specialized system-on-chip VLSI of COFDM (Coded Orthogonal Frequency Division Multiplex) for demodulator of a television signal of a terrestrial digital television
Development of technologically independent method of designing analog IC on the basis of library of parametrical cells
Development of the simulation environment of inertial navigation systems
Device-technological and circuit models of BiCMOS transistors, made on silicon-germanium technology
Device-technological simulation of SiGe bipolar and MOS transistor VLSI structures
Device for calculation of vector dot product with error correction based on residue number system
Diagnostic facilities and configurable digital systems on crystal portable integration
Digital Adaptive Linearization of Sensors for Technological Processes
Digital Linearization of Power Amplifier Amplitude Characteristic by Adaptive Inverse Modeling
Digital Signal Processor With Non-Conventional Recurrent Data-Flow Architecture
Digital Television Decoder VLSI. The Technology of Design
Digital circuit IBIS-models generation with account for temperature and radiation
Digital kernels of sigma-delta ADC/DAC and technology of their designing
Digital radiohologram hardware-in-the-loop simulation and processing for spaceborne SAR ground tests
Digital recursive generator of the samples of chirp
Digital sigma-delta modulator
Digital signal processing in airborne weather radar
Distributed multi lane serial links for multiprocessor systems interconnects
Distributed system and switching circuits optimization methods for Boolean functions of small number of variables
Dual-Core Heterogeneous System-on-Chip “Elbrus-2S+”
Dual-beam technology application for phase change nonvolatile RAM array prototyping
Dual core ASIC - System On Chip K1867BÖ3AÔ for advanced electronic equipments
Dynamic management of computations in distributed systems
Dynamic model for memory cell on tunnel magnetoresistance effect
Dynamics of Magnetization in the Free Layer of a Spin Valve Under the Influence of Magnetic Field, Perpendicular and Parallel to the Layer Plane
Efficiency of adaptive signal processing algorithms implementation on basis of MULTICORE SoC
Elbrus-8C: the first Russian 28 nm 8-core processor
Electro-Thermal Simulation of Multi-channel Power Devices: From Workbench to Simplorer by means of Model Reduction
Electro-thermal Simulation of a Bandgap
Electro-thermal modes simulation for PCB and IC in industrial class EDA environment
Electro-thermal simulation process implementation in Mentor Graphics IC Station
Electromigration Tolerance Improvement in Standard Cells
Electrostatic planar micromechanical relays
Electrostatic protection of BiCMOS IC's
End-to-end technology/device/circuit/system statistical design
Engineering Systems of Emulation Modules in KUB-PRO Form-factor
Enhancing subsystem for thermal simulation of PCB in Mentor Graphics EDA
Error control coding for submicron dynamic RAM
Estimation of CMOS VLSI hardness for high dose rate pulse irradiation
Estimation of ICs SEE Sensitivity Using Local Laser and Pulse Gamma-Ray Technique
Estimation of Single Event Effect Sensitivity Parameters by Local Laser Irradiation
Estimation of digital sensor's influence on the management systems efficiency
Ethernet Switch IP-core for Wireless Backhaul Systems
Evolutionary Algorithms of Test Generation for Crosstalk Faults of Digital Circuits
Evolutionary routing in the channel on the basis of symbolical representations
Evolution in the area of multicore heterogeneous video data processing systems
Experience in Self-Timed Microcontroller Core Design on Basic Gate-Array
Experience in design and modeling of analog circuits with limited parameters based on Russian bipolar technology
Experience of application of IP - blocks
Experience of application of a reduction of parasitic elements with use of subspace Krylov methods
Experience of designing built-in means and methods of characteristics measurement concerning microelectronic systems
Experience of development and methodology of designing mixed MES on an example high-speed 10-digit ADC
Experience of development of CCD matrix photoreceivers with interlower case carry
Experience of development of the high-speed matrix CCD, working in a mode of a time delay and accumulation of a charge
Experimental Project of the of VLSI Design Subsystem on the Basis of Hierarchical Client-Server Architecture
Experimental Verification of Some Laser Techniques' Approximations
Extended Drift-Diffusion Model of High-Speed Photodetectors for On-Chip Optical Interconnections
FPGA prototyping for functional verification of multi-core processors
FPGA reverse engineering by model-driven development
Family of domestic DSP-controllers "MultiCore" and elements of system interface "MultiCore-the designer" for construction of scaled parallel systems of teraflop productivity
Fast Affine Projection Algorithm: Full Version
Fault-tolerant systolic processor for digital signal processing in modular code
Fault tolerance increasing for access to network resources of MULTICORE series SoC for transparently distributed applications
Features of Limited Duration Harmonic Signal Transform by Sampling Theorem
Features of application ECC methods in sub-100 nm SRAMs for space systems
Features of constructions of specialized CCD matrixes
Features of designing of radiation-proof libraries of elements, complex-functional blocks and nano-VLSI SoC
Features of experimental research methods for memory with error correction
Features of magnetization reversal in a MRAM cell — I. In-plane anisotropy
Features of magnetization reversal in a MRAM cell — II. Perpendicular anisotropy
Features of processing and transmitting information in computing devices
Features of simulation of SiGe:C heterojunction bipolar transistor
Features of structurally functional construction of the precision intellectual microprocessor converter of the intellectual pressure sensor
Features of the design of analog circuits using transistors with low Early voltage
Features of the design of devices based on AlGaN/GaN heterostructures in technology computer aided design
Features of the radiation hardness evaluation for integrated circuits in specialized protective packages
Femtosecond Laser System for VLSI Heavy Ion Induced Single Event Effects Hardness Testing
Finite state machine state splitting for power minimization
Flip-flops and Drivers for High-Speed Current-Steering CMOS DACs
Flip Chip package design for sophisticated ASIC under small lot production
Floating point and complex arithmetic coprocessors and their verification
Forecasting of parametres of technical object by means of the intellectual microprocessor module
Formation and Verification of Standard Element Libraries in the Design Flow for the Domestic FPGAs
Formulation of the stability criterion of the third order IIR digital filters in the space of coefficients of the denominator of transfer function
Framework for mathematical simulation of multi-discipline technical systems and objects in time domain FMS PA10
Fully Integrated Switched-Capacitor DC/DC Converter
Functional Test for Graphics Controller
0.5 um SOI CMOS for Extreme Temperature Applications
Gate nets routing in nanometer standard cells with ports placement
Generalized Fading Models in Cognitive Radio Networks
Generating the test program for mixed-signal integrated circuits using the automata network
Generation of Initial Partitions for Hypergraph Balanced Cut Problem
Generation of large sets of logical functions for digital integrated circuits CAD systems
Genetic search at construction of connecting trees at a design stage of VLSI layout
Global placement algorithm for structured ASIC
Global routing accounting time restrictions and route-making resources
Graphs of communications and placement of nodes in "networks-on-chip"
Gyro-free inertial navigation system
Hardware-software complex for researching static characteristics of analog-digital converters
Hardware acceleration of digital simulation
Hardware implementation of FIR filter based on number-theoretic fast Fourier transform in residue number system
Hardware streams synchronization methods for multicore cluster
Heuristics of netless final layout of unrouted nets in the commutational block
High-frequency low-noise CMOS amplifier
High-speed content addressable memory block design
High-speed modules of integer division
High level model based verification of digital circuits behavior
History, Theory and Practice of Adaptive Signal Processing
Homogeneity Lot of Integrated Circuit Inspection based on Radiofrequency Measurement
Huffman encoder IP-core for JPEG image compression
Hybrid Bioinspired Algorithm for Forming Standard Cell Lines in the Design of the VLSI Topology
Hybrid method of memory allocating in multibank platforms based on the DSP NeuroMatrix architecture
Hybrid methods of time-domain analysis of electronic circuits
I-V Characteristics Calculation Model of SiC Based Nanoscale Mosfet With Deep Impurities and Trap Levels
IP-Core "ACC_Cores" as part system-on-chip. Multifunctional hardware accelerator Fast Fourier Transform - FFT_RT_Core
IP-Core SD Device Development
IP-block of the digital-to-analog converter with autocalibration
IP-core of High-Speed Low-Power ADC for multi-channel SoC
IP and Processor Cores Design for Navigation Application
IR photosensitive MEMS elements
IR voltage drop and Electromigration Aware Wire Sizing Algorithm
Image compression by using tensor approximation
Impact of ionizing radiation on GaN HEMTs
Implementation of Residue Number Systems Converter Combined with the Rounding Operation for DSP Applications
Implementation of SHF OA in limited BiCMOS basis
Implementation of the combustion problem main functions based on specialized vector coprocessor FMA operations
Improving the efficiency of the design integrated circuits on FPGA with limited resources to trace
Improving the efficiency of the tensor approximation for image compression by using the trained dictionary
Increase of efficiency of realization of digital filters in PLIC
Increase of uniformity of distribution of a thermal field at initial placement of topological IC cells
Increasing the Speed of a Multi-bit Binary Multiplier
Inexact operation prediction scheme realized in multiply-add fused module
Influence Reduction of Technological Variations and Interferences on Signal Distortion in High-Speed Integrated ADC for System-on-Chip
Influence of CMOS Hall Effect Sensor Layout on its Magnetic Sensitivity
Influence of parasitic parameters on the characteristics SAR ADC with switched capacitor DAC
Information problems of supervision and control in a micromechanical gyroscope system
Infrared focal plane arrays (FPA) with thermopile thermal radiation MEMS sensors
Initial placement of digital logic cells in integrated circuits considering net priority
Input stage of differential and multidifferential operational amplifiers with high common-mode rejection
Instruction scheduling for vector processors with variable vector length
Integrated S-band 6-bit Vector-Sum Phase Shifter with Decreased Phase Error
Integrated Step Up/Down Power Converter With Dynamic Control Of Clock Frequency
Integrated digital 6-bit attenuator for 8-12 GHz band
Integration of logic synthesis with a binding to library on the basis of universal systems of functions and direct methods of the generalized decomposition
Integration of logic synthesis with binding to library in system Integro
Interconnect Verification Methods Based on Unified Test Infrastructure
Inverter-based pseudo-flash ADC with low power consumption
Investigation and optimization of technological parameters of formation of the logical structure of the cells on "Silicon on Insulator"
Investigation of depencencies of high voltage SOI-MOSFETs safe operating area on structual and process-dependent parameters
Investigation of single event upset reliability for SOI CMOS SRAM cells using mixed-mode 3D TCAD-SPICE simulation
Investigation of the influence dispersion of technological parameters of VLSI on resistance to TID effects by device-technological simulation
Investigation of the possibilities of practical application of the adiabatic logic to reduce power consumption of VLSI
Key features of static timing analysis and SDC development for complex system-on-chip ASIC with multiple asynchronous clock domains
LMS adaptive filtering algorithm: first or unique one for practical applications?
Latency Analysis in Microarchitectural Models of Communication Fabrics
Lattice adaptive filtering algorithms is a new component of applied library for “Multicore” VLSI signal controller
Layout of microelectronic means on the basis of the multilevel approach
Leakage Power IC Optimization without RTL Changing
Level Quantization Impact on Accuracy of Fast Fourier Transform Algorithm
Level quantization effects in spectral analysis based on discrete Fourier transform
Library of applied functions in structure of MCStudio™ environment for development of the software "system-on-chip" of series "MULTICORE"
Linear Synthesis of k-valued Digital Structures: Principle of Generalization
Linear synthesis - a new approach to the logical design of k-valued digital structures
Logic-timing analysis methodology for characterization of custom blocks of digital CMOS IC
Logical timing analysis of digital IC reliability with NBTI and HCI degradation effects
Low-Power Synthesis of Logical CMOS Circuits
Low-Sensitivity Active RC-filter of the Second Order with an Extended Frequency Range
Low-discharge fully-coded multiplier for radar image synthesis systems
Low-noise Charge Sensitive Amplifiers for Hybrid Pixel Detec-tors
Low Power Driven Optimization of Two-Level Logic Circuits
Low power FSM’s synthesis based on combined structural model
“MULTICORE” platform IP-library of SoC peripherals
MCam-01 mixed signal multimedia processor
MEMS structures in receiving radio signals systems
MSV-driven VLSI floorplanning
Mathematical model for complex digital circuits and microsystems projects debugging based on presenting the latest as a family of stationary dynamical systems
Mathematical modelling of temperature distribution in thermal microsensors
Mathematical simulation of electromigratory faulures of interlayer connection of VLSI
Matrix multiplication of n-bit fixed point numbers via n/2-bit vector instructions
Means of Automating the Hierarchical Design of Complex Microelectronic Circuits with Uncertainty of Design Rules
Mechanisms of Multiple Cell Upsets in Memory
Membrane-based thermal flow sensor working on calorimetric principle
Memory testing algorithms for microprocessor board radiation test
Memristor oscillator Schmitt trigger with multiple steady states of dynamic equilibrium
Method and means of built-in self-testing of memory chip
Method for Binary and Vector Polynomial Expansion of Boolean Functions
Method for Organizing the Moore Automaton with the Increased Resistance to Soft Failures
Method for Reducing the Dimension of Training Sets at Constructing Neuromorphic Fault Dictionary for Analog Integrated Circuits
Method of Improving the Stability of Zero Analog Circuits with High-Impedance Node in the Conditions of Temperature and Radiation Effects
Method of QR-decomposition of a complex matrix by means of triangular systolic array
Method of automation of process of development of the crossbar for multicore system whith nonuniform memory access
Method of calculation of integrated resistors of I/O cells of IC with code adjustment of the nominal value
Method of construction of restrictions for an expanded set of technological rules
Method of mathematical testing of programs for transient analysis in EDA packages
Method of multisegment approximation of calibrating characteristics for precision calculations of pressure in intellectual sensors
Method of optimum curtailing of the scheme. The effective approach for the qualitative solution for non-polynomial combinatory problems of the large and superlarge dimensions in automated designing microelectronic devices
Method of placement blocks of three dimensional integration IC
Method of rule checks of electromigration in VLSI
Method of simulation of dynamics of technical systems on the basis of formal schemes
Method of small-signal analysis for the simulation of multitone radio frequency circuits
Methodologies problems of the processes CAD to design electronic component basis of the special purpose for radiation resistance evaluation
Methodology for creating design-for-test for CMOS VLSI
Methodology of designing of radiation-proof circuits on the basis of BMC for space vehicles
Methodology of designing of specialized calculators on the basis of the automated generation of technologically independent IP-blocks
Methodology of the automated designing of radio receiver devices of digital communication systems
Methodology of the optimization and efficiency evaluation for the Secondary Cache
Methods and algorithms of the decision of the differential-algebraic equations for modelling dynamics of technical systems and objects
Methods electromigration analysis conducting lines using the accelerated measurement test structures located in the wafer
Methods for Computation Planning in the Parallel Dataflow Computing System "Buran"
Methods for providing resilience to single chip developments in the design of radiation-resistant microcircuits
Methods of Achieving Test Scenario Portability Between Different Verification Environments
Methods of Scalar Products Speed Enhancement in Residue Logarithmic Number System Basis
Methods of compensation of basic components of the output capacitance of transistors in analog chips
Methods of designing custom IP-blocks based on the elements with regular topological structure in layers of polysilicon and diffusion
Methods of determination the coefficients of quasi-optimal FIR-filter for convolution of pseudorandom binary sequence
Methods of high-frequency correction for analog sections in ultrafast ADCs with differential input
Methods of implementation of high-speed serial channels CMOS transceivers on a physical level
Methods of increase of productivity of the superscalar RISC-processor
Methods of matched filtering radar broadband signals with minimum time delays
Methods of optimization of synthesized processor cores at realization of system-on-chp on the basis of FPGA
Methods of power delivery system noise immunity improvement in system on chip “Elbrus-S”
Methods of regulation of computation in parallel dataflow computating system
Methods of statistical timing analysis of digital circuits
Methods of structurally-parametrical synthesis of output cascades of tuned operational amplifiers for complex functional blocks
Methods of the parasitic extraction of interconnect in the integral circuits
Methods to control the hardness of specialized VLSI to space natural ionizing radiation
Methods to improve efficiency of microprocessor model stochastic tests
Methods to improve the gain of the classical stages on bipolar transistors at low supply voltage
Metrological problems of spectral estimation of varying process parameters and methods for their solution by means of modern computer technology
MicroTESK-Based Test Program Generator for the RISC-V Architecture
Microcircuitry of analog interfaces of electrochemical impedance spectroscopy systems
Microcontroller Ê1874ÂÅ96Ò. First russian 16-bit microconverter
Microcontroller 1830ÂÅ32Ó – 8-bit MSC-51 architecture in radhard style
Microwave quadrature demodulators. Development results
Microwave quadrature demodulators. Topology development results
Miniature and highly sensitive proximity infrared sensor
Minimization of the average number of conversion cycles of a successive approximation ADCs
Minimization of undesired layout patterns during standard cell synthesis
Model Order Reduction Techniques with Preservation of Sparseness in Circuit Simulation
Modeling TID leakage current in MOS-structures under x-ray and gamma irradiation
Modeling and Nonlinearity Research of the Segmented DAC
Modeling and Verification of Communication Fabrics in System on Chip Design
Modeling memristor circuits
Modeling of graphene electronics analog devices
Modeling of plasma-chemical etching technology in CF4/H2 mixture
Modeling of plasma-chemical etching technology in RF discharge
Modeling of the charge gathering from the heavy charged particles influence in CMOS integrated circuit
Modelling of frequency response of optomechanical thermal microsensors
Modelling of radio engineering circuits with digital modulation within the frames of VHDL-AMS simulation systems
Models and methods for SoC verification
Models of passive devices with the distributed parameters for the time domain analysis of nonlinear radio-frequency circuits
Modern adaptive signal processing: problems and solutions
Modern design tools of microelectronic circuits and systems-on-chip from the company ANSYS and ANSOFT. Overview of the features of Ansoft Designer, HFSS, Q3D Extractor, SIWAVE
Modernized design methodology blocks complex software and hardware systems with regard to their reliability parameters
Modern methods of functional verification RTL-models blocks for VLSI microprocessor
Modern tools of compilation of device models from high level language Verilog-A to internal representation of system Spectre
Modern trends in evaluating and monitoring of microprocessor performance at the design stage
Modulation Transfer Function Model for Photosensitive VLSI Under One Single Impact Particle Event
Motion Estimation IP-core Implementation for H.264 Full HD Video Codec
Multi-dimensional multirate systems and their implementation on different element base
Multi-layer global routing by a method of collective adaptation
Multi-pipelined architecture of high-performance crypto-blocks for using in “Systems on a Chip”
Multichannel adaptive lattice filters
Multicriteria approach to automation of radio networks planning
Multiprotocol switchboards for the heterogeneous distributed onboard complexes
NAND Flash memory controller IP-core
Nano-dimensional effect at planar inductance with “conducting film inside current ring”-technology
Nano-electromechanical thermo-sensitive elements
Nanometer merged MOS devices modeling
Nanostructured superconducting film concentrator in the magnetic field sensor
Narrow-band adaptive filtration in systems of digital processing signals
New Algorithm for the 2D Capacitance calculation in the interconnect parasitic extraction problem
New digital signal processor 1879ÂÌ4 of the NeuroMatrix® processor family
New generation of X-ray detectors on pixel array
New issues in application of diamond crystals in microelectronics and nanotechnologies
New methods of construction of microelectronic digital systems with low power consumption
New model of a threshold voltage of short-channel SiC MOS with deep impurity and capture levels
Noise analysis of digital circuits with accounting of logic constraints
Non-Stable Single Event Latch-up
Non-linear optimization framework for cell placement legalization
Nonlinear Phase Macromodel for the Analysis of oscillator circuits
Nonlinear modes in multidifferential operational amplifiers
Normative documents for designing "system-on-chip" and IP-blocks
Numerical Simulation of N-well MOSFET Hall Element
Numerical Simulation of Photosensitive VLSI Pixels
Numerical model for MISFETs characterization
Numerical model of semiconductors with crystal heating
Numerical simulation of solar radiation transmittance for textured surface silicon photovoltaic cells
On-board flight control system based on the MIPS architecture with CorExtend user-defined instructions and hardware-accelerated trigonometry calculations
On-chip Standard Cell Delay Verification Techniques
On Minimal Time of Process of Circuit Optimisation
One dimensional process and device simulation using spreadsheets
On one method of defining functional coverage metrics for microprocessor testing
On the Joint Application of the Matrix Method and the Apparatus of Generalized Powers of Bers for Mathematical Modeling of Heat and Mass Transfer in Semiconductor Materials of Electronic Engineering
Operational amplifiers with generalized current feedback
Optical Receiver Architecture for Microprocessor Systems
Optimal design of the MEMS thermopile element for an IR imager array
Optimization Procedures in the Analog Circuit CAD System
Optimizational transformations of VHDL-models of digital systems
Optimization for some phase of Komdiv64-RIO design flow
Optimization methods of coding circuits based on the binary decision diagrams for synthesis of fault-tolerant micro- and nanoelectronic circuits
Optimization of Capacitor Based DAC
Optimization of TSMC 28nm Physical and Logical VLSI Design Flow
Optimization of VLSI Regular Power Grid
Optimization of instrumentation amplifiers structures with indirect current feedback instrumentation amplifiers
Optimization of structure of controllers of serial buses. The solution of problems of lack of pins of a integrated circuit and loading of the processor at data transmission
Optimization of structure of processing and commutation of video information digital streams in multichannel systems
Optimization of technological regimes of manufacturing a bipolar heterotransistors
Optimization of the breakdown voltage in IGBT structure on the base of its constructive and technology parameters
Optimized for Sub-micron Processes A High Speed ADC Architecture
Optimizing the prefetch mechanism in the secondary cache memory
Organization of instruction pipeline in ELcore-õxTM DSP-cores of “MULTICORE” IP-library
Package ZUBR of the automated designing of digital circuits on the basis of programmed logic integrated schemes
Parallel VLSI Layout Decomposition Algorithm for Double Patterning
Parallel computing in the ring of Gaussian integers over the Galois field GF(p)
Parameter optimization subsystem of CMOS operational amplifiers
Parameters extraction of the scaled MOS-transistor model
Partitioning Algorithm Based on Simulated Annealing for Reconfigurable Systems-on-Chip
Partitioning methods for Large-Scale Equivalence Checking and Function Correction
Peculiarities in methods of designing power supply systems in high-performance microprocessors at the stage of physical design of the crystal
Peripheral analog-digital blocks for CMOS VLSI of type "system-on-chip"
Perturbation methods and selective methods in problems of a reduction of high-dimension models
Phisical Design Flow optimization for Komdiv64-RIO processor
Photoconductive Switch for MmWave Substrate Integrated Waveguide (SIW)
Photosensitive CCD: state-of-the-art and development perspectives
Photosensitive CCD VLSI TCAD modeling
Physical-topological model of modulation transfer fuction
Physical and Topological Simulation of Photodetectors for AIIIBV Integrated Optical Commutation Systems Taking into Account Dependence of Charge Carriers Mobilities on Electric Field
Physical and chemical model of memory and switching effects in thin-film CdSe1-xTex elements
Pipeline Depth Influence on DSP Performance
Pipeline structure optimization according to performance criterion for DSP-core with Harvard architecture
Pipelining and parallelization: two approaches to rise computational performance
Placement of Logic Cells of Integrated Circuits with Simultaneous Consideration of Performance and Thermal Mode
Placement of nodes in a heterogeneous network-on-crystal
Polygons size and form optimization in layout compaction process
Polynomial modular multipliers for error correcting code devices
Possibilities of The distributed subsystem topological design, built on the basis of client-server technologies
Powering the Directed VLSI Firmware and Software Testing with Data Flow Aware Limited Branch Alternation
Practical Aspects of Design Verification of Complex Chips
Practical Aspects of Formal Verification of Networking Chips
Practical developments and projects for substitution of import and IP-projects on base of radiation-resistant analog array chip
Precision instrumentation amplifiers
Precision sensor conditioners for mixed SoC
Preliminary Processing of Experimental Data in Statistical Integrated Circuit Design
Principles of Constructing a System of Logic Simulation with Consideration of Destabilizing Factors
Principles of Designing Devices for Test Diagnosing of High-speed Microchips and Semiconductor Memory
Principles of construction of specialized calculators based on residual arithmetics
Probabilistic approximation of a location problem
Probabilistic methods for reliability evaluation of combinational circuits
Problem of a transistor length variation in a standard cell at multi-objective optimization of nano-size VLSI
Problems of Designing LDMOS-transistors Working at Increased Supply Voltage
Problems of creation of computers of series "Baguet" for problems with increased requirements to reliability of long-term functioning
Problems of platform approach for System on Chip and IP cores test infrastructure creation and their solutions
Problems of using device-technological simulation as tool of designing and ways of their solution
Procedure of automated MCU selection for design of electronic and computer technology products
Procedures of Channel Rooting on the Basis of Hybridization of Swarm Intelligence with Genetic Search
Process and device simulation of CMOS SOI VLSI elements with an account for radiation effects
Processing speed increase and hardware cost reduction in Hsiao decoders
Programmable High Frequency PLL Divider
Prospects of using SiGe BiCMOS technology for creation of the SHF circuits
Prospects of using submicronic CMOS VLSI in failure-proof equipment working under impact of atmospheric neutrons
Proton and gamma-radiation ionizing effect comparative results
Prototyping linux kernel drivers in userspace with lua scripting language
Pseudo-differential cascode output buffer for high-speed serial data transmission across a channel with high losses
Pulse-potential type ADC in CMOS-basis for mixed-signal SoC
Quadrature modulators for engineering process SGB25VD. Development results
Quasi-Delay-Insensitive Computing Device: Methodological and Algorithmic Aspects
Quasi Self-Timed Computing Device: Practical Implementation
Quasi optimal in time algorithm of designing of analog circuits
RF-frontend Parts of Remote Sensing Systems Synthesis Method
RF IP-blocks based on Fully differential OpAmps for Communication Systems
Radar Image Autofocus in Conditions of High Vehicle Motion Instability
Radiation-hardned CMOS VLSI SRAM in bulk technology
Radiation-resistant instrumentation amplifiers for ABMC
Radiation Resistance of MEMS Sensors and Methods of Its Estimation
Radiation hardened EEPROM structures integrated with SOI CMOS techology
Radiation hardened analog IC
Radiation hardened analog IC design. Part 1. Radiation effects simulation in the "Spice-like" programs
Radiation hardened analog IC design. Part 2. The main analog circuits for the master slice array "ABMK 1-3"
Radiation tolerant Hybrid for Multiplex Data Bus(RU Standard GOST R 52070-2003). New opportunities for spaceborne computers
Random Test Generator for Multicore Microprocessor Cache Coherence Verification (Ristretto)
Rank codec IP-core
Rank codes with partially known error basis
Rational Transfer Functions Approximation on the Base of Integral Accuracy Criterion
Rational composition of typical grading system for ASIC’s radiation hardness testing
Readout circuit from the nonvolatile memory
Recent software for VLSI operating in space radiation environment estimation analysis
Recognition and interpretation of erroneous behavior in simulation-based hardware verification
Reconfigurable Smart Sensor Controllers
Recovering Signal and Σ-Δ Modulator Parameters
Recurrent data-flow architecture: features and realization problems
Recurrent data-flow architecture: technical aspects of implementation and modeling results
Reducing area and increasing compression ratio of scan compression system for digital VLSI using stuck-at fault model
Reduction of influence of single interference in submicronic trigger memory cells
Register Duplication for Scan Compression Designs
Register file base elements and design flow development for SOI 0.25-micron technology
Reliability and Accuracy of ODE Systems Solution for Modeling Environment of Heterogeneous Dynamic Systems PA10
Reliability evaluation for SEU in cache in system-on-chip design
Research, development and optimization of data exchange hardware in multicore computing systems
Research and Development of Digital System Block Models Based on Their Description as a Stationary Dynamical System Family
Research and development of structural decisions of frequency synthesizers on the PLL basis
Research and development of structures for the extraction of circuit model parameters accounting dose radiation effects in submicron VLSI
Researching VLSI RAM 8Ê on the basis of SoS structures
Research of characteristics of artificial inductance on MOS transistors
Research of characteristics of electrically erasable programmable read-only memory for automobile electronics
Research of electric and temperature area of safe work of planar power SoC MOS transistors
Research of fully CMOS compatible EEPROM cell
Research of hardware implementation efficiency of discovering data dependences in coprocessor's pipeline of KOMDIV128-RIO processor
Research of influence of constructive-technology factors on sensitivity of magnetic transistor with methods of device-technological simulation
Research of methods and tools of verification of projects and generation of tests of microelectronic systems
Research of stability of process of optimization of analog circuits
Research of the RF performance of SiGe HBT during transition towards sub-100 nm technology limits
Research of the model of distributed topological VLSI design by means of the hierarchical client-server architecture
Research the principles of operation of the input block for the parallel dataflow computing system
Research ways to design a dynamic branch prediction unit for promising microprocessor development by SRISA RAS
Residue Logarithmic Number System – A New Possibilities for Residue Processors and Converters Designing
Resonant energy efficiency driver
Resource-aware Patch Generation of Boolean Circuits
Results of computer modelling of the decision of a problem of placing of elements VLSI taking into account time delays
Results of technological and devices modeling of the complementary bipolar technology with 10 GHz cutoff frequency and over
Reusable complex Soc level tests creating and debugging method
Route of designing "system-on-chip" on the basis of IP-libraries of a platform "MULTICORE"
Route of development and FPGA-verifications of IP-core of controller SpaseWire link for "system-on-chip" on the basis of platform "MultiCore"
Route of effective IC development
Route reconfiguration in RapidIO system in case of faulty connections
Routing of Memory Bits Cells with Automated Construction of Boundary Layout Constraints
Running OS Linux as a stage of functional testing of microprocessors
SADEL – extra precision solvers library for program suite PA10 (SADEL-PA10)
SATOK - System for Self-Timed Integrated Circuits Testing
SCIC designing of the frequency-voltage converter for the programmable voltage standard
SDF Report Generation Methodology for Digital Delay Lineswithout Simulations
SD Host Controller IP-core
SEE sensitive parameters estimation in VLSI using local laser technique
SEE sensitivity changes at different TID levels
SHF Devices Correction by Circuits of High Order
SOI MOSFET Compact SPICE model for radiation-hardened 0.35 µm IC design
SPICE-Models of Field-Effect Transistors with MOSFET and JFET Structures in the Temperature Range down to –200°C
SPICE Simulation of CMOS Circuits Behavior for Extreme Ambient Applications Using “Electro-Thermo-Rad” models
SPICE models of optoelectronic elements for simulation of photosensitive PD-CMOS VLSI
SRAM memory controller to maximize switch performance
Sampling theorem applied to data interpolation problem
Scalable DSP Multiprocessor
Scalable diode macromodel with high modeling accuracy
Schematic-topological design of VLSI cells
Segment calibration in pipeline ADC
Self-Timed Computing Device for High-Reliable Applications
Self-Timed Floating Point Multiply-Add Unit
Self-compensation of small-signal parameter influence in stages on CMOS transistors
Self-testing of complex functional blocks
Self-timed D-trigger with «Load/Latch»
Self Compensation in Spectrum Limiters with Extended Operating Frequency Range
Semi-Natural MOSFET Compact Model
Set of integrated circuits designed to control power transistor switches
Shortest trees construction on the basis alternatives field crystallization method
Si BJT and SiGe HBT TCAD simulation taking into account radiation effects
Sigma-delta ADC for capacitive accelerometer
Signal Seepage Impact on the Matched Filtration Results in Radar with Continuous Emission
Simulation at the level of transactions for system designing and debugging of systems-on-crystals
Simulation configuration changes and data processing channels in the system in a contingency situation
Simulation modeling for survivability evaluation of digital control systems
Simulation of Circuits with Ferroelectric Capacitances
Simulation of MEMS Technology Based Thermoelectric Generators
Simulation of Magnetization Dynamics in Three-layered Ferromagnetic Structures with Pinned Boundaries
Simulation of PLL Perturbation Based on Blocks Transfer Functions
Simulation of SEU failures in submicronic SoS CMOS cells of memory in view of temperature effects
Simulation of SEU transients in CMOS 28-nm DICE cells subject to single-event multi-node charge collection
Simulation of processes of equilibrium and fast heat treatments at formation of the active areas of submicronic and nanomicronic ICs
Simulation of transistor structures of power electronics
Simulation of unsteady modes of thermal microsensors
Single-Event Upset Simulation of the 65 nm 6T CMOS Static Memory Cells
Single Event Latchup and Catastrophic Failure in CMOS Devices Investigation and Prevention Methods
Single Event Rate Evaluation for Modern ICs
Single Precision Reciprocal and Inverse Square Root Functions Modules
Singularity of radiation-hardened amplifiers circuitry based on BiMOS ABMC
SoC focused technologies of brain-like quantum computing
SoC protocols specification and validation: problems and solutions
Software & Hardware based Navigation Solutions for Mobile Devices
Software package for Technology Computer-Aided Design of spintronic devices based on magnetic tunneling junctions
Spaceborne SAR spatial resolution and radiometric characteristic determination using a method of echo signal digital simulation
Special features and results of designing the family of LVDS CMOS 0,25/0,18/0,13 ìm drivers and receivers
Specialized the architecture of the parallel multicore dataflow computing system for solution of task FFT
Specification-Based Test Program Generation for MIPS64 Memory Management Units
Speed-Independent Fused Multiply-Add Unit of Gigaflops Rating: Implementation Variants
Speed-Independent Fused Multiply-Add Unit of Gigaflops Rating: Methodological Aspects
Splitting on the basis of multilevel parallel evolutionary adaptation
Spread spectrum clock generator design methods
SsVER - system of synthesis and verification of combinational logic schemes
Standalone verification of microprocessors using reference models with various levels of abstraction
Standard Cell Routing via Boolean Satisfiability
Standard cell characterezition methodoligy with respect MOSFET threshold voltage variation
Standard cell libraries content optimization
Static and Dynamic Error of Current-Steering DACs
Static timing analysis aware false conduct path detection in terms of logic implication
Statistical approach to multiple cell upsets description in highly scaled memory circuits
Statistical timing analysis aware of reconvergence of conduction paths and transition variations
Structural optimization and development of the monolithic IC SiGe active attenuator
Structure and Algorithm Development of Built-in Self-repair for SRAM
Structure of control vector by optimization of analog circuits
Study of mapping processor for dataflow parallel computing system "Buran"
Submicron CMOS digital elements with elevated performance stability from the impact of atmospheric neutrons
Subsystem of CAD for synthesis of the encoder/decoder IP-cores for convolution turbo codes
Superconducting Film Concentrator of the Magnetic Field with Nanoscale Branches
Support methods of reliability on the wireless sensor networks by criterion of the network load
Survey on features of integrated antennas
Synchronization of active radar target simulator for SAR tests
Synchronous elastic circuits design and its application for H.264 CABAC decoder performance optimization
Synthesis external interrupt controller with dynamically change the priority
Synthesis of Recursive Digital Filters with Finite Word Length: Problems and Their Solutions
Synthesis of memory units using a description of design rules via Boolean functions of layout objects
Synthesis of substrate models of SoC
Synthesis of topology of standard CMOS cells taking into account effect of electromigration
System Debugging Tools for Recurrent Computing Device
SystemVerilog assertions for verification and imitating modelling
SystemVerilog object-oriented programming features for functional verification of multi-core SoC
System approach to design UHF RFID reader transceiver ICs
System for parallel processing of mobile operator traffic
System level design of the DSP processor IP-core with NeuroMatrix architecture
System of Combined Specialized Test Generators for the New Generation of VLIW DSP Processors with Elcore50 Architecture
System of Compaction and Migration of Standard Cell Layouts
TCAD-model of CCD image sensor with vertical antiblooming
TCAD simulation of nanometer MOSFET on the assumption of the surface roughness at Si/SiO2 interface
Technique of characterization of ROM-compiler using controlled current sources
Technologies for Building Scalable Prototypes of Server Microprocessors
Technology migration of CMOS band gap voltage reference
Technology of debugging "system-on-chip" of series "MULTICORE"
Technometric Identification of Integrated Circuits for Controlling Life Cycle and Counterfeit Detection
Temperature sensors modeling for smart power ICs
Tendencies of development of crystal CAD systems
Test and Computer Simulation Procedure for Single Event Effect Prediction of ICs in a Space Environment
Test automation tool for the computing unit of the recurrent operational level
Testing and limiting metrological possibilities of pulse-potential ADC in SoC
Testing the Performance of the Embedded Gigabit Ethernet Controller’s FPGA Prototype when working with TCP
The "Multicore" series processors features for signal processing in modern multifunctional radar
The "Sensor microsystem on crystal": the sensor interface simulation
The Application of Single-step High Order Integration Methods for Periodic Steady-state Analysis of Integrated Circuits
The Bivalent Defect of Modular Codes. The Choise of Technological Modules, that Reduce Bivalent Defect
The Characterization Flow and Simulation Method of Frequency Synthesizer
The DICE cells layout design for the hardened CMOS 28 nm SRAM
The Design of Current Memory Elements Based on the Mathematical Tool of Linear Algebra
The Development of the Method for Analyzing Mutual Synchronization Mode of Oscillators in Integrated Circuits
The Electromagnetic Interferences From Display Device on Capacitive Touch Panel
The Energy of the Bound State of Zero Radius Impurity Center in a Quantum Wire in External Electric and Magnetic Fields
The Experience of Universal Controller SSD Development for Space Application
The Functional Method of the Analysis of Speed-Independent Circuits of Any Size
The Gate Delay Analysis Method Accounting for Simultaneous Input Switching
The Instrumentation and Differential Difference Amplifiers of Sensor Systems Based on the New Microcircuit of the Structured Array MH2XA010
The Method of Section Approximation for Grid Optimization for Standard Cell Library Characterization
The Methods of Fast Characterization of Large Scale Integration Parameterized IP-blocks
The Numerical Algorithm for Stability Analysis of Large Dynamical Systems
The RLNS Implementation for matrix algebra special problems solution
The Results of the Implementation of the Copy Function on a Vector Coprocessor
The Rip-up and Reroute Technique Research for Physical Synthesis in the Basis of Reconfigurable SoCs
The Single Event Upset Forecasting in Digital and Analog Integrated Circuits in SAED 14nm FinFet Technology
The Symmetrized Memristor Relaxation Oscillator
The Technique for Implementing a Neural Network for Recognizing Handwritten Digits in FPGAs Based on Fixed Point Calculations
The Technological Flow for Special SOP Rad-hard ICs Manufacturing
The Technology of Manufacturing of Complementary Transistors on Gallium Nitride
The Utilization of Photolayers for Bipolar Transistors Implementation in Typical CMOS Process
The advanced algorithms of comparison of graphs of electric circuits
The algorithm for synthesis of digital ICs based on the Gilbert decomposition
The analysis of dynamic processes of interference distribution in substrates of integrated elements with methods of device-technological simulation
The analysis of operability ùà submicronic RAM CMOS VLSI at extreme thermal modes
The application and implementation issues of dataflow computing system
The approach to investigation of analog ICs radiation hardness
The architecture of a cluster of the distributed intelligence system of collection and processing of signals of sensors of physical quantities
The architecture of scheduler of mapping processor of PDCS "Buran"
The block of digital operative processing ùà matrix thermovisual photoreceiver on the basis of the signal microcontroller
The block of self-testing of internal memory
The built-in DSCA block with interface AMBA AHB
The capabilities of usage virtual platforms for verification of RTL-models of complex co-processor blocks
The circuitry of electronic devices that operate in conditions of electromagnetic noise
The comparative analysis of circuit simulation models of SiGe heterojunction transistor
The complete set of complex-functional blocks for systems of processing and transfer of videoimages
The computational method for nonlinear distortion analysis with multitone test signals
The conceptual approach to construction of the device of visualization of three-dimensional images in format OpenGL on processors of a series "Multicore"
The controller of the laser smoke fire detector with frequency filtering
The decision of problems of optimization and designing of schemes of electronic computers on the basis of use of hybrid intellectual methods
The dynamic extreme parameters of operational amplifiers with voltage feedback and amplifiers with current feedback in linear and nonlinear modes
The environment of development of the software for "system-on-chip" of series "MULTICORE" MCStudio_Lnx
The features of automated design of derangements generators
The general properties and modifications of reduction algorithms
The implementation of channels of DDR4 RAM for microprocessor "Elbrus-8Ñ2"
The logical elements of comparison for the sub-100 nm CMOS selectors of associative memory
The magnetic tunnel junction model for circuit design systems
The main parameters and equations of basic configurations multidifferential operational amplifiers with high impedance node
The means for computation distribution in the PDCS "Buran" and the implementation variants of a block of hash-functions
The method for CMOS APS light-voltage characteristics technological-device modeling
The method for photosensitive matrix VLSI modulation transfer function simulation
The method of EFSM extraction from HDL: application to functional verification
The method of computing theoretical bounds on the performance of DVFS controllers in MPSoC
The method of harmonic balance for electrothermal analysis of periodic steady states of IC
The method of peak current estimation at logic level taking into account simultaneous switching of inputs
The method of static power reducing for CMOS circuits based on sleep transistors with operation speed control
The method of timing optimization for FPGA at the microarchitecture level using the pipelining mechanism
The methodology of the automated generation and analysis of basic structures for the design of dynamic and static protection the blocks of integrated circuits against ESD
The methods of time-logic analysis of library elements and VLSI blocks for advanced technologies with a vertical transistor’s gate
The mixed systems on a crystal for systems of automatic control of technical diagnostics
The modeling and design of the MIC LNA with the built-in antenna for the 57-64 GHz bandwidth on GaN
The modeling of NBTI effect in analog integrated circuits
The organisation of the synchronously-asynchronous decision of problems of gathering and processing of the information of gauges in intellectual microprocessor modules
The parametric optimization and the automatic tuning for digital state regulators
The position sensor IC based on a photoreceiving ruler with reading on a CCD with hidden channel
The power effective communication line for systems on a crystal with dynamic management of frequency synchronization
The principle of factorization in a problem of design of RBS-based processors
The problems of reconfigurable computer systems application for processing of UHDTV signals
The process flow simulation of the cathode-grid system and its emission properties
The project of the on-chip processor for videostream processing are developed. This project are based on Russian SIMD processor PARS
The reduction algorithms of linear networks with inductances on the base of selective methods of elimination
Thermal simulation of MES components: from submicronic VLSI elements up to complex electronic blocks
Thermo Researching of X-band Microwave Amplifier
Thermoelectric Generator for Human Body Monitoring Systems
The simulation method of nonlinear distortion of radio frequency circuits with digital modulation in circuit simulators
The single event transient simulation of the two-phase CMOS inverters for sub-100-nm standards
The static accuracy model for the pipelined ADC with calibration
The subsystem for processing structure-functional descriptions of circuits in a CAD system
The technique of logical circuit parameters selection in nanometer RHBD CMOS VLSI
The technique of test generator realization for built-in self-test circuitries
The two-phase 28-nm CMOS inverters in SET-tolerant logics
The usage of dataflow computing model and architecture realizing these for exaflops performance system
The use of VHDL models of partial Boolean functions for the design of digital circuits
The way design for testability of logical transformers
Timing analysis of digital circuits basing on logic correlations
To creation of the domestic concept of systems on a crystal
Tool amplifiers on the basis of multidifferential OAs
Tracing of change in a condition of dynamic object in real time with use of the microprocessor module
Transistor placement at standard cell level
Trends in development of content addressable memory architectures and its application in the parallel dataflow computing system
Tunable electric polarization of amorphous ferromagnetic wires at GHz frequencies for wireless sensing applications
Two-Parameter Model for Estimation SEE Sensitivity of VLSI under Ion Irradiation
Two-dimensional Adaptive Antenna Arrays in Complex-valued and Real-valued Arithmetic
Two-level evolutional-genetic routing of electric circuits on graph models
Two-level reduction of models of parasitic circuits of the high order
Two current mirrors - twice bandgap
UVM using for an autonomous verification of digital hardware
Unified approach to radiation hardness assurance of high-speed ASICs
Universal scan based JTAG compatible VLSI debug structure
Universal technique of estimation of roundoff noise of IIR filters, described by topological matrixes
Use of parallel computing in VLSI computer-aided design
User programmed logical cores for creation system-on-chip
User programmed system-on-chip
Using Formal Coverage Analyzer for Code Coverage Improvement
Using TCAD in designing the planar powerful MOS-transistors having the raised breaking-down voltage in the off-state
Using clusterization in logical synthesis
Using convertible addressing modes to improve performance of DSP co-processors in a multicore SoC
Using of VBIC model for SiGe integrated circuit application
Using the gate capacitance of MOS transistor as LPF's capacitance and its impact on the PLL's characteristics of quality
Utilization of fine-grained parallelism in dataflow processor
VHDL-Simulation-Based Evaluation of CMOS-Circuits Power Consumption
VLSI microprocessor monitoring unit
Variable-length code packing IP-core
Variants of realization of controller for parallel dataflow computing system to work with vector and multioperand nodes
Various Radio System Signal Digital Simulation and Analysis by Means of the Hardware-in-the-loop Experimental Tryout Complex
Verification of Logical Descriptions of Combinational Circuits
Verification of Memory Requests Arbitration Algorithm
Verification of Sampling Theorem Validity and Features for Specific Cases of Transformed Samples Number
Verification of divers systems based on integrated circuits
Virtual Tests of Micro- and Nanoelectronic Systems on External Influences
Virtualizing IO devices
Voltage References on FET Differential Pairs with control pn-transition
Voltage reference on the basis of an analog base matrix crystal
Voronoi diagram based graph models building in VLSI physical design
Ways of creation intellectual sensors of pressure used for substitution of import ones
Web-based Generation of Highlevel Models of Digital Cells
Web-based automatic generation of input patterns at characterization of digital cells
Wideband Multichannel 60 GHz Switches in 90 nm CMOS Process
Working out and application problems nano - and the microsystem technique in perspective products of space technics
Yield enhancement of standard cell layout
14b SAR ADC with ODC Background Calibration
16-digit 6.4 MHz CMOS sigma-delta ADC for sound processing
1879ÕÊ1 System-on-a-Chip for digital processing of analog signals in radio systems and satellite navigation systems
28nm IC’s Parameters Optimization without RTL Changing
3D flexible microwave polyimid T-line assembly for system in package
64-bit superscalar embedded RISC microprocessor

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