Home         Authors   Papers   Year of conference   Themes   Organizations        To MES conference


Listing of works with the partition by the subject of reports. Click on the work title to see its details. The selected set may be restricted by specifying a range of conference years, or by selecting a specific topic.

Select: from to year
All topics

ADC design problems
Cellular automata
Design of System-on-chip (SoC) and IP-blocks
Design of VLSI elements
Design of VLSI signal processors
Design of analog and mixed functional blocks of VLSI
Design of digital functional blocks of VLSI
Design of fault-tolerance systems
Design of micro-electromechanical systems
Design of nanoelectronic devices
Design of nanoelectronic devices based on Josephson junctions
Design of photodetecting VLSI
Design of radiation-resistant VLSI
Design of technological processes
Designing components for aerospace and navigation technology
Genetic algorithms in VLSI CAD
Methods and algorithms for automated layout design
Methods for high-level simulation
Methods of device technology simulation of VLSI
Methods of digital information processing and digital filters
Methods of electro-thermal simulation
Methods of logic synthesis and functional logic simulation ...
Methods of simulation of VLSI electrical characteristics
Models of devices for circuit simulation
Problems of development of sensory microcircuitry
Simulation of data transfer channels
Study of the magnetic properties of materials
Unconventional computing systems
design of memory cells
Selection on topic: Methods of logic synthesis and functional logic simulation in VLSI CAD
Selected papers: from 2005 to 2018 year
In selection - 66 papers
ASPECT Ė a Subsystem of Event Analysis of Self-Timed Circuits
Algebraic Decomposition Models for Digital System Design Debugging by Simulation
A parallel critical path algorithm with loop detection for static timing analysis of sequential circuits
Application of standard cell characterization results in statistical timing analysis
CMOS circuit interval static timing analysis accounting for logic correlations
Characterization of pseudodynamic elements
Complex platform of functional verification of Mentor Graphics
Computer-aided design of topology of functional blocks of custom digital VLSI
Conditional jump re-alternation Limiting based speed-up of Directed Automated program testing
Decomposition and Minimization of Binary Decision Diagrams for Systems of Specified Boolean Functions
Decomposition of Boolean Functions for BDD
Decomposition on the basis of universal systems of functions and its application at logic and topological VLSI synthesis
Definition of competence areas of synthesis algorithms of combinational logic circuits
Delay Insensitive Circuits for Low Power and Highly Reliable Microprocessors
Delay noise analysis, using graph of constraint pairs
Designing of regular circuits with consecutive connections of transistors
Designing on FPGA of high-speed finite state machines
Development Principles of Debugging Tools for Recurrent-Computing Device
Distributed system and switching circuits optimization methods for Boolean functions of small number of variables
FPGA reverse engineering by model-driven development
Features of processing and transmitting information in computing devices
Finite state machine state splitting for power minimization
Generation of large sets of logical functions for digital integrated circuits CAD systems
High level model based verification of digital circuits behavior
Integration of logic synthesis with a binding to library on the basis of universal systems of functions and direct methods of the generalized decomposition
Integration of logic synthesis with binding to library in system Integro
Investigation of the possibilities of practical application of the adiabatic logic to reduce power consumption of VLSI
Latency Analysis in Microarchitectural Models of Communication Fabrics
Linear Synthesis of k-valued Digital Structures: Principle of Generalization
Linear synthesis - a new approach to the logical design of k-valued digital structures
Logical timing analysis of digital IC reliability with NBTI and HCI degradation effects
Low-Power Synthesis of Logical CMOS Circuits
Low Power Driven Optimization of Two-Level Logic Circuits
Low power FSMís synthesis based on combined structural model
Method for Binary and Vector Polynomial Expansion of Boolean Functions
Method of optimum curtailing of the scheme. The effective approach for the qualitative solution for non-polynomial combinatory problems of the large and superlarge dimensions in automated designing microelectronic devices
Methods of statistical timing analysis of digital circuits
Noise analysis of digital circuits with accounting of logic constraints
Optimizational transformations of VHDL-models of digital systems
Partitioning methods for Large-Scale Equivalence Checking and Function Correction
Principles of Constructing a System of Logic Simulation with Consideration of Destabilizing Factors
Running OS Linux as a stage of functional testing of microprocessors
Scalable diode macromodel with high modeling accuracy
SoC focused technologies of brain-like quantum computing
SsVER - system of synthesis and verification of combinational logic schemes
Static timing analysis aware false conduct path detection in terms of logic implication
Statistical timing analysis aware of reconvergence of conduction paths and transition variations
Subsystem of CAD for synthesis of the encoder/decoder IP-cores for convolution turbo codes
Test automation tool for the computing unit of the recurrent operational level
The Functional Method of the Analysis of Speed-Independent Circuits of Any Size
The Gate Delay Analysis Method Accounting for Simultaneous Input Switching
The algorithm for synthesis of digital ICs based on the Gilbert decomposition
The features of automated design of derangements generators
The method of peak current estimation at logic level taking into account simultaneous switching of inputs
The method of static power reducing for CMOS circuits based on sleep transistors with operation speed control
The methods of time-logic analysis of library elements and VLSI blocks for advanced technologies with a vertical transistorís gate
The use of VHDL models of partial Boolean functions for the design of digital circuits
The way design for testability of logical transformers
Timing analysis of digital circuits basing on logic correlations
Use of parallel computing in VLSI computer-aided design
Using clusterization in logical synthesis
VHDL-Simulation-Based Evaluation of CMOS-Circuits Power Consumption
Verification of Logical Descriptions of Combinational Circuits
Web-based Generation of Highlevel Models of Digital Cells
Web-based automatic generation of input patterns at characterization of digital cells
28nm ICís Parameters Optimization without RTL Changing

Copyright © 2009-2018 IPPM RAS. All Rights Reserved.

Design of site: IPPM RAS