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Listing of works with the partition by the subject of reports. Click on the work title to see its details. The selected set may be restricted by specifying a range of conference years, or by selecting a specific topic.

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ADC design problems
Cellular automata
Design of System-on-chip (SoC) and IP-blocks
Design of VLSI elements
Design of VLSI signal processors
Design of analog and mixed functional blocks of VLSI
Design of digital functional blocks of VLSI
Design of fault-tolerance systems
Design of micro-electromechanical systems
Design of nanoelectronic devices
Design of nanoelectronic devices based on Josephson junctions
Design of photodetecting VLSI
Design of radiation-resistant VLSI
Design of technological processes
Designing components for aerospace and navigation technology
Genetic algorithms in VLSI CAD
Methods and algorithms for automated layout design
Methods for high-level simulation
Methods of device technology simulation of VLSI
Methods of digital information processing and digital filters
Methods of electro-thermal simulation
Methods of logic synthesis and functional logic simulation ...
Methods of simulation of VLSI electrical characteristics
Models of devices for circuit simulation
Problems of development of sensory microcircuitry
Simulation of data transfer channels
Study of the magnetic properties of materials
Unconventional computing systems
design of memory cells
Selection on topic: Design of VLSI elements
Selected papers: from 2005 to 2018 year
In selection - 39 papers
A 14-bit 100 MS/s Pipelined ADC
An adaptive random search algorithm for parametric identification of electronic components’ models
Analysis of Distortions Caused by Impulses in Switching Transistors Sources in Current-Steering DAC
Automation of synthesis of VHDL-AMS models for the mixed and analog behavioural simulation
Converting VLSI macroblock structure by regrouping uniform function blocks
Debugging and testing of VLSI models with use of the prototypes realized on PLIC
Designing of custom-made blocks taking into account extraction RC parasitic parameters
Designing on FPGA and SoC high-performance binary comparators of a big dimensionality
Development and designing of integrated thermoelements
Development of microwave phase shifter based on SOI 0.18-micron technology
Dual-beam technology application for phase change nonvolatile RAM array prototyping
Electrostatic protection of BiCMOS IC's
Estimation of digital sensor's influence on the management systems efficiency
Fully Integrated Switched-Capacitor DC/DC Converter
Homogeneity Lot of Integrated Circuit Inspection based on Radiofrequency Measurement
Integrated S-band 6-bit Vector-Sum Phase Shifter with Decreased Phase Error
Integrated digital 6-bit attenuator for 8-12 GHz band
Memristor oscillator Schmitt trigger with multiple steady states of dynamic equilibrium
Methodologies problems of the processes CAD to design electronic component basis of the special purpose for radiation resistance evaluation
Methods of the parasitic extraction of interconnect in the integral circuits
Microcircuitry of analog interfaces of electrochemical impedance spectroscopy systems
Nano-dimensional effect at planar inductance with “conducting film inside current ring”-technology
Nanometer merged MOS devices modeling
Preliminary Processing of Experimental Data in Statistical Integrated Circuit Design
Reduction of influence of single interference in submicronic trigger memory cells
Register file base elements and design flow development for SOI 0.25-micron technology
SRAM memory controller to maximize switch performance
Schematic-topological design of VLSI cells
Simulation of SEU transients in CMOS 28-nm DICE cells subject to single-event multi-node charge collection
Single-Event Upset Simulation of the 65 nm 6T CMOS Static Memory Cells
Standard cell libraries content optimization
Survey on features of integrated antennas
Synchronous elastic circuits design and its application for H.264 CABAC decoder performance optimization
Temperature sensors modeling for smart power ICs
The Utilization of Photolayers for Bipolar Transistors Implementation in Typical CMOS Process
The logical elements of comparison for the sub-100 nm CMOS selectors of associative memory
The methodology of the automated generation and analysis of basic structures for the design of dynamic and static protection the blocks of integrated circuits against ESD
The methods of time-logic analysis of library elements and VLSI blocks for advanced technologies with a vertical transistor’s gate
The single event transient simulation of the two-phase CMOS inverters for sub-100-nm standards

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