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Themes

Listing of works with the partition by the subject of reports. Click on the work title to see its details. The selected set may be restricted by specifying a range of conference years, or by selecting a specific topic.

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All topics

ADC design problems
Cellular automata
Design of System-on-chip (SoC) and IP-blocks
Design of VLSI elements
Design of VLSI signal processors
Design of analog and mixed functional blocks of VLSI
Design of digital functional blocks of VLSI
Design of fault-tolerance systems
Design of micro-electromechanical systems
Design of nanoelectronic devices
Design of nanoelectronic devices based on Josephson junctions
Design of photodetecting VLSI
Design of radiation-resistant VLSI
Design of technological processes
Designing components for aerospace and navigation technology
Genetic algorithms in VLSI CAD
Methods and algorithms for automated layout design
Methods for high-level simulation
Methods of device technology simulation of VLSI
Methods of digital information processing and digital filters
Methods of electro-thermal simulation
Methods of logic synthesis and functional logic simulation ...
Methods of simulation of VLSI electrical characteristics
Models of devices for circuit simulation
Problems of development of sensory microcircuitry
Simulation of data transfer channels
Study of the magnetic properties of materials
Unconventional computing systems
design of memory cells
Selection on topic: Genetic algorithms in VLSI CAD
Selected papers: from 2005 to 2018 year
In selection - 11 papers
ABDGHMPST
A 
 
Adoption of Genetic Algorithms for running in elastic compute environment concerning CAD applications
Algorithms of evolutionary swarm intelligence for solving graph partition problem
Ant algorithm for determining the critical linkages in VLSI
B 
 
Bioinspired VLSI chip planning methods
D 
 
Development of Methods for Genetic Synthesis of Fault-Tolerant Logic circuits
G 
 
Genetic search at construction of connecting trees at a design stage of VLSI layout
H 
 
Hybrid Bioinspired Algorithm for Forming Standard Cell Lines in the Design of the VLSI Topology
M 
 
Method of placement blocks of three dimensional integration IC
P 
 
Problem of a transistor length variation in a standard cell at multi-objective optimization of nano-size VLSI
S 
 
Splitting on the basis of multilevel parallel evolutionary adaptation
T 
 
Two-level evolutional-genetic routing of electric circuits on graph models

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