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Themes

Listing of works with the partition by the subject of reports. Click on the work title to see its details. The selected set may be restricted by specifying a range of conference years, or by selecting a specific topic.

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All topics

ADC design problems
Cellular automata
Design of System-on-chip (SoC) and IP-blocks
Design of VLSI elements
Design of VLSI signal processors
Design of analog and mixed functional blocks of VLSI
Design of digital functional blocks of VLSI
Design of fault-tolerance systems
Design of micro-electromechanical systems
Design of nanoelectronic devices
Design of nanoelectronic devices based on Josephson junctions
Design of photodetecting VLSI
Design of radiation-resistant VLSI
Design of technological processes
Designing components for aerospace and navigation technology
Genetic algorithms in VLSI CAD
Methods and algorithms for automated layout design
Methods for high-level simulation
Methods of device technology simulation of VLSI
Methods of digital information processing and digital filters
Methods of electro-thermal simulation
Methods of logic synthesis and functional logic simulation ...
Methods of simulation of VLSI electrical characteristics
Models of devices for circuit simulation
Problems of development of sensory microcircuitry
Simulation of data transfer channels
Study of the magnetic properties of materials
Unconventional computing systems
design of memory cells
Selection on topic: Models of devices for circuit simulation
Selected papers: from 2005 to 2018 year
In selection - 32 papers
ACDFIMNPRSTU
A 
 
Accuracy Improvement of the Interconnect Parasitic Capacitance Extraction
C 
 
Calculation 2D inductance for extraction problems
Calculation of inductance in problems of designing superconductive microelectronic structures
D 
 
Device-technological simulation of SiGe bipolar and MOS transistor VLSI structures
Dynamic model for memory cell on tunnel magnetoresistance effect
F 
 
Features of processing and transmitting information in computing devices
Features of simulation of SiGe:C heterojunction bipolar transistor
I 
 
Influence of CMOS Hall Effect Sensor Layout on its Magnetic Sensitivity
M 
 
Method of calculation of integrated resistors of I/O cells of IC with code adjustment of the nominal value
Modeling of graphene electronics analog devices
Models of passive devices with the distributed parameters for the time domain analysis of nonlinear radio-frequency circuits
N 
 
New Algorithm for the 2D Capacitance calculation in the interconnect parasitic extraction problem
New model of a threshold voltage of short-channel SiC MOS with deep impurity and capture levels
Nonlinear Phase Macromodel for the Analysis of oscillator circuits
Numerical Simulation of Photosensitive VLSI Pixels
Numerical model for MISFETs characterization
Numerical model of semiconductors with crystal heating
P 
 
Parameters extraction of the scaled MOS-transistor model
R 
 
Research of characteristics of artificial inductance on MOS transistors
Research of electric and temperature area of safe work of planar power SoC MOS transistors
S 
 
SOI MOSFET Compact SPICE model for radiation-hardened 0.35 µm IC design
SPICE-Models of Field-Effect Transistors with MOSFET and JFET Structures in the Temperature Range down to –200°C
SPICE Simulation of CMOS Circuits Behavior for Extreme Ambient Applications Using “Electro-Thermo-Rad” models
SPICE models of optoelectronic elements for simulation of photosensitive PD-CMOS VLSI
Semi-Natural MOSFET Compact Model
Simulation of SEU failures in submicronic SoS CMOS cells of memory in view of temperature effects
Synthesis of substrate models of SoC
T 
 
The comparative analysis of circuit simulation models of SiGe heterojunction transistor
The magnetic tunnel junction model for circuit design systems
Two-level reduction of models of parasitic circuits of the high order
U 
 
Using of VBIC model for SiGe integrated circuit application
Using the gate capacitance of MOS transistor as LPF's capacitance and its impact on the PLL's characteristics of quality

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