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Themes

Listing of works with the partition by the subject of reports. Click on the work title to see its details. The selected set may be restricted by specifying a range of conference years, or by selecting a specific topic.

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ADC design problems
Cellular automata
Design of System-on-chip (SoC) and IP-blocks
Design of VLSI elements
Design of VLSI signal processors
Design of analog and mixed functional blocks of VLSI
Design of digital functional blocks of VLSI
Design of fault-tolerance systems
Design of micro-electromechanical systems
Design of nanoelectronic devices
Design of nanoelectronic devices based on Josephson junctions
Design of photodetecting VLSI
Design of radiation-resistant VLSI
Design of technological processes
Designing components for aerospace and navigation technology
Genetic algorithms in VLSI CAD
Methods and algorithms for automated layout design
Methods for high-level simulation
Methods of device technology simulation of VLSI
Methods of digital information processing and digital filters
Methods of electro-thermal simulation
Methods of logic synthesis and functional logic simulation ...
Methods of simulation of VLSI electrical characteristics
Models of devices for circuit simulation
Problems of development of sensory microcircuitry
Simulation of data transfer channels
Study of the magnetic properties of materials
Unconventional computing systems
design of memory cells
Selection on topic: Design of radiation-resistant VLSI
Selected papers: from 2005 to 2018 year
In selection - 67 papers
ACDEFIMNPRSTU
A 
 
ADC for radiation-proof IP blocks
Application of a technique of not destroying control of dose stability of parties SoS CMOS VLSI
Application of quasi-hydrodynamic model for the analysis of electronic transport in field and bipolar transistors in conditions of a pulse ionizing radiation in view of the raised temperatures
Appraisal of constructive-technological capabilities improvement of radiation hardening deep sub-micron VLSI
Automated Picosecond Laser Facility for Single Event Effects Simulation in Microelectronic Devices under Space Environment
Autonomous parameters of of transistors of uncommited logic array ABMK_1_3 in radiation and temperature influences
C 
 
CMOS 65-nm static RAM on DICE cells with spacing groups of transistors
Circuitry design features of radiation-resistant IC ABMC
D 
 
Dependence of MCU Sensitivity in SRAM on Data Pattern and angle of incident
Digital circuit IBIS-models generation with account for temperature and radiation
E 
 
Estimation of CMOS VLSI hardness for high dose rate pulse irradiation
Estimation of ICs SEE Sensitivity Using Local Laser and Pulse Gamma-Ray Technique
Estimation of Single Event Effect Sensitivity Parameters by Local Laser Irradiation
Experimental Verification of Some Laser Techniques' Approximations
F 
 
Features of designing of radiation-proof libraries of elements, complex-functional blocks and nano-VLSI SoC
Features of experimental research methods for memory with error correction
Features of the radiation hardness evaluation for integrated circuits in specialized protective packages
Femtosecond Laser System for VLSI Heavy Ion Induced Single Event Effects Hardness Testing
I 
 
Impact of ionizing radiation on GaN HEMTs
Investigation of single event upset reliability for SOI CMOS SRAM cells using mixed-mode 3D TCAD-SPICE simulation
Investigation of the influence dispersion of technological parameters of VLSI on resistance to TID effects by device-technological simulation
M 
 
Mechanisms of Multiple Cell Upsets in Memory
Memory testing algorithms for microprocessor board radiation test
Method of Improving the Stability of Zero Analog Circuits with High-Impedance Node in the Conditions of Temperature and Radiation Effects
Methodologies problems of the processes CAD to design electronic component basis of the special purpose for radiation resistance evaluation
Methodology of designing of radiation-proof circuits on the basis of BMC for space vehicles
Methods for providing resilience to single chip developments in the design of radiation-resistant microcircuits
Methods to control the hardness of specialized VLSI to space natural ionizing radiation
Microcontroller 183032 8-bit MSC-51 architecture in radhard style
Modeling TID leakage current in MOS-structures under x-ray and gamma irradiation
Modeling of the charge gathering from the heavy charged particles influence in CMOS integrated circuit
N 
 
New generation of X-ray detectors on pixel array
P 
 
Practical developments and projects for substitution of import and IP-projects on base of radiation-resistant analog array chip
Process and device simulation of CMOS SOI VLSI elements with an account for radiation effects
Prospects of using submicronic CMOS VLSI in failure-proof equipment working under impact of atmospheric neutrons
Proton and gamma-radiation ionizing effect comparative results
R 
 
Radiation-hardned CMOS VLSI SRAM in bulk technology
Radiation hardened EEPROM structures integrated with SOI CMOS techology
Radiation hardened analog IC
Radiation hardened analog IC design. Part 1. Radiation effects simulation in the "Spice-like" programs
Radiation hardened analog IC design. Part 2. The main analog circuits for the master slice array "ABMK 1-3"
Radiation tolerant Hybrid for Multiplex Data Bus(RU Standard GOST R 52070-2003). New opportunities for spaceborne computers
Rational composition of typical grading system for ASICs radiation hardness testing
Recent software for VLSI operating in space radiation environment estimation analysis
Research and development of structures for the extraction of circuit model parameters accounting dose radiation effects in submicron VLSI
Researching VLSI RAM 8 on the basis of SoS structures
S 
 
SEE sensitive parameters estimation in VLSI using local laser technique
SEE sensitivity changes at different TID levels
SOI MOSFET Compact SPICE model for radiation-hardened 0.35 m IC design
Si BJT and SiGe HBT TCAD simulation taking into account radiation effects
Simulation of SEU transients in CMOS 28-nm DICE cells subject to single-event multi-node charge collection
Single-Event Upset Simulation of the 65 nm 6T CMOS Static Memory Cells
Single Event Latchup and Catastrophic Failure in CMOS Devices Investigation and Prevention Methods
Singularity of radiation-hardened amplifiers circuitry based on BiMOS ABMC
Statistical approach to multiple cell upsets description in highly scaled memory circuits
Submicron CMOS digital elements with elevated performance stability from the impact of atmospheric neutrons
T 
 
Test and Computer Simulation Procedure for Single Event Effect Prediction of ICs in a Space Environment
The DICE cells layout design for the hardened CMOS 28 nm SRAM
The Instrumentation and Differential Difference Amplifiers of Sensor Systems Based on the New Microcircuit of the Structured Array MH2XA010
The Technological Flow for Special SOP Rad-hard ICs Manufacturing
The approach to investigation of analog ICs radiation hardness
The logical elements of comparison for the sub-100 nm CMOS selectors of associative memory
The single event transient simulation of the two-phase CMOS inverters for sub-100-nm standards
The technique of logical circuit parameters selection in nanometer RHBD CMOS VLSI
The two-phase 28-nm CMOS inverters in SET-tolerant logics
Two-Parameter Model for Estimation SEE Sensitivity of VLSI under Ion Irradiation
U 
 
Unified approach to radiation hardness assurance of high-speed ASICs

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