Home         Authors   Papers   Year of conference   Themes   Organizations        To MES conference

Themes

Listing of works with the partition by the subject of reports. Click on the work title to see its details. The selected set may be restricted by specifying a range of conference years, or by selecting a specific topic.

Select: from to year
 
All topics

ADC design problems
Cellular automata
Design of System-on-chip (SoC) and IP-blocks
Design of VLSI elements
Design of VLSI signal processors
Design of analog and mixed functional blocks of VLSI
Design of digital functional blocks of VLSI
Design of fault-tolerance systems
Design of micro-electromechanical systems
Design of nanoelectronic devices
Design of nanoelectronic devices based on Josephson junctions
Design of photodetecting VLSI
Design of radiation-resistant VLSI
Design of technological processes
Designing components for aerospace and navigation technology
Genetic algorithms in VLSI CAD
Methods and algorithms for automated layout design
Methods for high-level simulation
Methods of device technology simulation of VLSI
Methods of digital information processing and digital filters
Methods of electro-thermal simulation
Methods of logic synthesis and functional logic simulation ...
Methods of simulation of VLSI electrical characteristics
Models of devices for circuit simulation
Problems of development of sensory microcircuitry
Simulation of data transfer channels
Study of the magnetic properties of materials
Unconventional computing systems
design of memory cells
Selection on topic: ADC design problems
Selected papers: from 2005 to 2018 year
In selection - 41 papers
ACDEFGHIMOPRST1
A 
 
A 2-bit Flash ADC for Pipeline Circuits
A 8-bit flash ADC with reduced DNL
A 14-bit 100 MS/s Pipelined ADC
ADC for radiation-proof IP blocks
A High Speed ADC with Low Power Consumption
AMS components design for System in Package
A Pipelined Analog-to Digital Converters With Digital Calibration
A Precision Voltage-to-Frequency Converter Design
An 8-bit segmented DAC with high conversion rate
Analog-digital "system-on-chip" MF01 of series "Multiflex"
Analog-digital VLSI of a high-speed frequency synthesizer on SiGe BiCMOS 0,25 mkm technology
Analog-digital interfaces of the mixed systems on a crystal
Analysis of Distortions Caused by Impulses in Switching Transistors Sources in Current-Steering DAC
Analysis of Distortions Caused by Output Capacitance Modulation in Current-Steering DAC
C 
 
Ceramics-based device of touch and contactless information input for avionics
D 
 
DAC capacity optimization for OFDMA modulation
Design of behavioral model of sample and hold circuit based on the results of chip testing
Digital sigma-delta modulator
E 
 
Experience of development and methodology of designing mixed MES on an example high-speed 10-digit ADC
F 
 
Flip-flops and Drivers for High-Speed Current-Steering CMOS DACs
G 
 
Generating the test program for mixed-signal integrated circuits using the automata network
H 
 
Hardware-software complex for researching static characteristics of analog-digital converters
I 
 
IP-block of the digital-to-analog converter with autocalibration
IP-core of High-Speed Low-Power ADC for multi-channel SoC
Influence Reduction of Technological Variations and Interferences on Signal Distortion in High-Speed Integrated ADC for System-on-Chip
Influence of parasitic parameters on the characteristics SAR ADC with switched capacitor DAC
Inverter-based pseudo-flash ADC with low power consumption
M 
 
Methods of high-frequency correction for analog sections in ultrafast ADCs with differential input
Microcontroller 187496. First russian 16-bit microconverter
Minimization of the average number of conversion cycles of a successive approximation ADCs
Modeling and Nonlinearity Research of the Segmented DAC
O 
 
Optimized for Sub-micron Processes A High Speed ADC Architecture
P 
 
Pulse-potential type ADC in CMOS-basis for mixed-signal SoC
R 
 
Research and development of structural decisions of frequency synthesizers on the PLL basis
S 
 
Segment calibration in pipeline ADC
Sigma-delta ADC for capacitive accelerometer
Static and Dynamic Error of Current-Steering DACs
T 
 
Testing and limiting metrological possibilities of pulse-potential ADC in SoC
The static accuracy model for the pipelined ADC with calibration
1 
 
14b SAR ADC with ODC Background Calibration
16-digit 6.4 MHz CMOS sigma-delta ADC for sound processing

Copyright 2009-2019 IPPM RAS. All Rights Reserved.

Design of site: IPPM RAS