Home         Authors   Papers   Year of conference   Themes   Organizations        To MES conference


Listing of works with the partition by the subject of reports. Click on the work title to see its details. The selected set may be restricted by specifying a range of conference years, or by selecting a specific topic.

Select: from to year
All topics

ADC design problems
Cellular automata
Design of System-on-chip (SoC) and IP-blocks
Design of VLSI elements
Design of VLSI signal processors
Design of analog and mixed functional blocks of VLSI
Design of digital functional blocks of VLSI
Design of fault-tolerance systems
Design of micro-electromechanical systems
Design of nanoelectronic devices
Design of nanoelectronic devices based on Josephson junctions
Design of photodetecting VLSI
Design of radiation-resistant VLSI
Design of technological processes
Designing components for aerospace and navigation technology
Genetic algorithms in VLSI CAD
Methods and algorithms for automated layout design
Methods for high-level simulation
Methods of device technology simulation of VLSI
Methods of digital information processing and digital filters
Methods of electro-thermal simulation
Methods of logic synthesis and functional logic simulation ...
Methods of simulation of VLSI electrical characteristics
Models of devices for circuit simulation
Problems of development of sensory microcircuitry
Simulation of data transfer channels
Study of the magnetic properties of materials
Unconventional computing systems
design of memory cells
Selection on topic: Design of fault-tolerance systems
Selected papers: from 2005 to 2018 year
In selection - 10 papers
Analysis Based on TCAD Simulation of Failure Tolerance of the Elements on the Cells STG DICE for 65-nm CMOS Blocks of Associative Memory
CMOS 65-nm static RAM on DICE cells with spacing groups of transistors
Design of the error-correcting code blocks using the two-phase CMOS logic elements
Features of experimental research methods for memory with error correction
Optimization methods of coding circuits based on the binary decision diagrams for synthesis of fault-tolerant micro- and nanoelectronic circuits
Probabilistic methods for reliability evaluation of combinational circuits
Reliability evaluation for SEU in cache in system-on-chip design
The circuitry of electronic devices that operate in conditions of electromagnetic noise
The logical elements of comparison for the sub-100 nm CMOS selectors of associative memory
The technique of logical circuit parameters selection in nanometer RHBD CMOS VLSI

Copyright 2009-2019 IPPM RAS. All Rights Reserved.

Design of site: IPPM RAS