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Listing of works with the partition by the subject of reports. Click on the work title to see its details. The selected set may be restricted by specifying a range of conference years, or by selecting a specific topic.

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ADC design problems
Cellular automata
Design of System-on-chip (SoC) and IP-blocks
Design of VLSI elements
Design of VLSI signal processors
Design of analog and mixed functional blocks of VLSI
Design of digital functional blocks of VLSI
Design of fault-tolerance systems
Design of micro-electromechanical systems
Design of nanoelectronic devices
Design of nanoelectronic devices based on Josephson junctions
Design of photodetecting VLSI
Design of radiation-resistant VLSI
Design of technological processes
Designing components for aerospace and navigation technology
Genetic algorithms in VLSI CAD
Methods and algorithms for automated layout design
Methods for high-level simulation
Methods of device technology simulation of VLSI
Methods of digital information processing and digital filters
Methods of electro-thermal simulation
Methods of logic synthesis and functional logic simulation ...
Methods of simulation of VLSI electrical characteristics
Models of devices for circuit simulation
Problems of development of sensory microcircuitry
Simulation of data transfer channels
Study of the magnetic properties of materials
Unconventional computing systems
design of memory cells
Selection on topic: Design of System-on-chip (SoC) and IP-blocks
Selected papers: from 2005 to 2018 year
In selection - 144 papers
A Method for Scalable Verification of PROMELA Models of Cache Coherence Protocols
Algebraic Decomposition Models for Digital System Design Debugging by Simulation
An 8-bit segmented DAC with high conversion rate
An Efficient Router Bufferization for Network-on-Chip Design
Analog-digital "system-on-chip" MF01 of series "Multiflex"
Analog-digital "system on crystal" peripheral controller MCT-01 on the basis of IP-libraries of a platform "MULTICORE"
Analysis of modern microprocessors peak performance
Application of packages of plate support as the tool of adaptation of specialized operational systems for functioning on platform "MULTICORE"
Applying OpenCL Technology to Vector Processor Design
Architecture of DSP-accelerators on the basis of a platform "MultiCore" for supercomputers of new generation
Architecture of domestic IC series of type "system or network on chip" on the basis of IP-libraries of platform "MULTICORE"
Architecture of fault-resistant FPGA with capacity over 100 thousand gates
Automated design of Networks-on-Chip with custom topology
Autonomous parameters of of transistors of uncommited logic array ABMK_1_3 in radiation and temperature influences
Block of Fast Fourier Transformation for wireless communication systems on the basis of
Block of decoder Viterbi for wireless communication systems on the basis of standard IEEE 802.16
Built-in self-repair for SRAM with redundant elements
CMOS frequency divider by 2 with high stability of output signal duty cycle
Characteristics of the "Multicore" series controllers for FFT processing signal in real time and their application in radar
Circuitry design features of radiation-resistant IC ABMC
Communication fabric IP-core for a system-on-chip
Comparative analysis of active mm-wave SiGe mixers
Compensation method of voltage references second order component temperature drift
Computer memory subsystem optimization by providing guaranteed memory bandwidth
Configurable IP-cores architecture analysys using criterion of implementation ability in “MULTICORE” platform IP-library
Controller IP-block for control functions realization in SoC
Creation of "system-on-chip" on the basis of PLIC with use of synthesized processor kernels
Design criteria of Frequency selection for the internal oscillator UHF RFID tags
Designing SoC on the basis of library of IP-blocks GRLIB of company Gaisler Research
Designing of custom-made blocks taking into account extraction RC parasitic parameters
Design tools of high-performance dataflow computing systems
Development of Methods for Architecturally-oriented Resynthesis in the Computer-aided Design Flow for FPGAs
Development of Real Number Models of Analog IP Blocks for Mixed Signal SoC Verification
Development of a monolithic IC receiver with a phase shifting is performed in the LO part
Development of behavioural cycle-accurate model of a system-on-chip with C++
Development of specialized VLSI of type "system-on-chip" for digital two-system navigating receiver GLONASS/GPS
Development of specialized system-on-chip VLSI of COFDM (Coded Orthogonal Frequency Division Multiplex) for demodulator of a television signal of a terrestrial digital television
Diagnostic facilities and configurable digital systems on crystal portable integration
Digital Television Decoder VLSI. The Technology of Design
Distributed multi lane serial links for multiprocessor systems interconnects
Dual-Core Heterogeneous System-on-Chip “Elbrus-2S+”
Dual core ASIC - System On Chip K1867BÖ3AÔ for advanced electronic equipments
Efficiency of adaptive signal processing algorithms implementation on basis of MULTICORE SoC
Elbrus-8C: the first Russian 28 nm 8-core processor
Evolution in the area of multicore heterogeneous video data processing systems
Experience of application of IP - blocks
Experimental Project of the of VLSI Design Subsystem on the Basis of Hierarchical Client-Server Architecture
FPGA prototyping for functional verification of multi-core processors
Family of domestic DSP-controllers "MultiCore" and elements of system interface "MultiCore-the designer" for construction of scaled parallel systems of teraflop productivity
Fault tolerance increasing for access to network resources of MULTICORE series SoC for transparently distributed applications
Forecasting of parametres of technical object by means of the intellectual microprocessor module
Formation and Verification of Standard Element Libraries in the Design Flow for the Domestic FPGAs
Graphs of communications and placement of nodes in "networks-on-chip"
Hardware streams synchronization methods for multicore cluster
High-speed modules of integer division
Huffman encoder IP-core for JPEG image compression
Hybrid method of memory allocating in multibank platforms based on the DSP NeuroMatrix architecture
IP-Core "ACC_Cores" as part system-on-chip. Multifunctional hardware accelerator Fast Fourier Transform - FFT_RT_Core
IP-Core SD Device Development
IP-core of High-Speed Low-Power ADC for multi-channel SoC
IP and Processor Cores Design for Navigation Application
Implementation of SHF OA in limited BiCMOS basis
Influence Reduction of Technological Variations and Interferences on Signal Distortion in High-Speed Integrated ADC for System-on-Chip
Interconnect Verification Methods Based on Unified Test Infrastructure
Library of applied functions in structure of MCStudio™ environment for development of the software "system-on-chip" of series "MULTICORE"
“MULTICORE” platform IP-library of SoC peripherals
MCam-01 mixed signal multimedia processor
Matrix multiplication of n-bit fixed point numbers via n/2-bit vector instructions
Means of Automating the Hierarchical Design of Complex Microelectronic Circuits with Uncertainty of Design Rules
Method of automation of process of development of the crossbar for multicore system whith nonuniform memory access
Methodology of designing of specialized calculators on the basis of the automated generation of technologically independent IP-blocks
Methods of optimization of synthesized processor cores at realization of system-on-chp on the basis of FPGA
Methods of power delivery system noise immunity improvement in system on chip “Elbrus-S”
Methods to improve the gain of the classical stages on bipolar transistors at low supply voltage
Microcontroller Ê1874ÂÅ96Ò. First russian 16-bit microconverter
Modeling and Verification of Communication Fabrics in System on Chip Design
Models and methods for SoC verification
Modern design tools of microelectronic circuits and systems-on-chip from the company ANSYS and ANSOFT. Overview of the features of Ansoft Designer, HFSS, Q3D Extractor, SIWAVE
Modern trends in evaluating and monitoring of microprocessor performance at the design stage
Multi-dimensional multirate systems and their implementation on different element base
Multiprotocol switchboards for the heterogeneous distributed onboard complexes
New digital signal processor 1879ÂÌ4 of the NeuroMatrix® processor family
New methods of construction of microelectronic digital systems with low power consumption
Normative documents for designing "system-on-chip" and IP-blocks
On-board flight control system based on the MIPS architecture with CorExtend user-defined instructions and hardware-accelerated trigonometry calculations
Optimization of VLSI Regular Power Grid
Optimizing the prefetch mechanism in the secondary cache memory
Organization of instruction pipeline in ELcore-õxTM DSP-cores of “MULTICORE” IP-library
Partitioning Algorithm Based on Simulated Annealing for Reconfigurable Systems-on-Chip
Peculiarities in methods of designing power supply systems in high-performance microprocessors at the stage of physical design of the crystal
Peripheral analog-digital blocks for CMOS VLSI of type "system-on-chip"
Phisical Design Flow optimization for Komdiv64-RIO processor
Pipeline structure optimization according to performance criterion for DSP-core with Harvard architecture
Pipelining and parallelization: two approaches to rise computational performance
Placement of nodes in a heterogeneous network-on-crystal
Practical Aspects of Formal Verification of Networking Chips
Problems of platform approach for System on Chip and IP cores test infrastructure creation and their solutions
Procedure of automated MCU selection for design of electronic and computer technology products
Quasi-Delay-Insensitive Computing Device: Methodological and Algorithmic Aspects
Quasi Self-Timed Computing Device: Practical Implementation
Radiation-resistant instrumentation amplifiers for ABMC
Recurrent data-flow architecture: features and realization problems
Recurrent data-flow architecture: technical aspects of implementation and modeling results
Reliability evaluation for SEU in cache in system-on-chip design
Research, development and optimization of data exchange hardware in multicore computing systems
Research and development of structural decisions of frequency synthesizers on the PLL basis
Research ways to design a dynamic branch prediction unit for promising microprocessor development by SRISA RAS
Reusable complex Soc level tests creating and debugging method
Route of designing "system-on-chip" on the basis of IP-libraries of a platform "MULTICORE"
Route of development and FPGA-verifications of IP-core of controller SpaseWire link for "system-on-chip" on the basis of platform "MultiCore"
Route reconfiguration in RapidIO system in case of faulty connections
SD Host Controller IP-core
Scalable DSP Multiprocessor
Self-testing of complex functional blocks
Self Compensation in Spectrum Limiters with Extended Operating Frequency Range
SoC protocols specification and validation: problems and solutions
Software & Hardware based Navigation Solutions for Mobile Devices
Special features and results of designing the family of LVDS CMOS 0,25/0,18/0,13 ìm drivers and receivers
Specification-Based Test Program Generation for MIPS64 Memory Management Units
Standard cell libraries content optimization
Study of mapping processor for dataflow parallel computing system "Buran"
System level design of the DSP processor IP-core with NeuroMatrix architecture
Technologies for Building Scalable Prototypes of Server Microprocessors
Technology of debugging "system-on-chip" of series "MULTICORE"
Tendencies of development of crystal CAD systems
The Technological Flow for Special SOP Rad-hard ICs Manufacturing
The architecture of a cluster of the distributed intelligence system of collection and processing of signals of sensors of physical quantities
The built-in DSCA block with interface AMBA AHB
The complete set of complex-functional blocks for systems of processing and transfer of videoimages
The environment of development of the software for "system-on-chip" of series "MULTICORE" MCStudio_Lnx
The method of computing theoretical bounds on the performance of DVFS controllers in MPSoC
The mixed systems on a crystal for systems of automatic control of technical diagnostics
The power effective communication line for systems on a crystal with dynamic management of frequency synchronization
The problems of reconfigurable computer systems application for processing of UHDTV signals
The project of the on-chip processor for videostream processing are developed. This project are based on Russian SIMD processor PARS
The usage of dataflow computing model and architecture realizing these for exaflops performance system
To creation of the domestic concept of systems on a crystal
Trends in development of content addressable memory architectures and its application in the parallel dataflow computing system
User programmed logical cores for creation system-on-chip
User programmed system-on-chip
Using convertible addressing modes to improve performance of DSP co-processors in a multicore SoC
Utilization of fine-grained parallelism in dataflow processor
Variants of realization of controller for parallel dataflow computing system to work with vector and multioperand nodes
1879ÕÊ1 System-on-a-Chip for digital processing of analog signals in radio systems and satellite navigation systems

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