Home         Authors   Papers   Year of conference   Themes   Organizations        To MES conference


Listing of works with the partition by the subject of reports. Click on the work title to see its details. The selected set may be restricted by specifying a range of conference years, or by selecting a specific topic.

Select: from to year
All topics

ADC design problems
Cellular automata
Design of System-on-chip (SoC) and IP-blocks
Design of VLSI elements
Design of VLSI signal processors
Design of analog and mixed functional blocks of VLSI
Design of digital functional blocks of VLSI
Design of fault-tolerance systems
Design of micro-electromechanical systems
Design of nanoelectronic devices
Design of nanoelectronic devices based on Josephson junctions
Design of photodetecting VLSI
Design of radiation-resistant VLSI
Design of technological processes
Designing components for aerospace and navigation technology
Genetic algorithms in VLSI CAD
Methods and algorithms for automated layout design
Methods for high-level simulation
Methods of device technology simulation of VLSI
Methods of digital information processing and digital filters
Methods of electro-thermal simulation
Methods of logic synthesis and functional logic simulation ...
Methods of simulation of VLSI electrical characteristics
Models of devices for circuit simulation
Problems of development of sensory microcircuitry
Simulation of data transfer channels
Study of the magnetic properties of materials
Unconventional computing systems
design of memory cells
Selection on topic: Design of digital functional blocks of VLSI
Selected papers: from 2005 to 2018 year
In selection - 79 papers
A Library of Self-Timed Elements or ASIC-Technology
Adaptation of performance tests for the 64-bit universal superscalar microprocessor
Alarm controllers MS-0226 and ĚŃ-0226G on the basis of platform "MULTICORE"
A method for reducing timing delay temperature dependence of digital integrated circuits
Analysis of efficiency of complex use low-power techniques for blocks of digital VLSI
Architecture of the unified computing block for contactless photon system of measurement of parameters of a rail track
Architecture validation tests for RTL-model of 64-bit superscalar microprocessor
Arithmetical algorithms of the coding system of 1 from 4 with an active zero and estimation of the parameters of high-speed performance and occupied area of the unit of summation
Built-in self-repair for SRAM with redundant elements
“Cycle-To-Cycle” methodology for timing analysis of high speed synchronous interfaces
CAVLC encoder IP-core for H.264/AVC
Clock Tree Synthesis Optimization
Common approaches to the FPU verification
Communication fabric IP-core for a system-on-chip
Complex arithmetic coprocessor
Debugging of the block of transformation of addresses of the microprocessor
Design a functional model of FPGA whith single-driver technology in Xilinx ISE system
Designing on FPGA and SoC high-performance binary comparators of a big dimensionality
Design of Power Efficient 14-port Register File and Translation Lookaside Buffer in 28-nm Process
Design of Self-Timed Circuits: a Functional Approach
Design of digital CMOS circuits for extreme temperatures
Design of the error-correcting code blocks using the two-phase CMOS logic elements
Design of the hybrid CAM register
Development of integral digital filters for sigma-delta converters using MATLAB
Digital Signal Processor With Non-Conventional Recurrent Data-Flow Architecture
Error control coding for submicron dynamic RAM
Experience in Self-Timed Microcontroller Core Design on Basic Gate-Array
FPGA prototyping for functional verification of multi-core processors
Features of designing of radiation-proof libraries of elements, complex-functional blocks and nano-VLSI SoC
Floating point and complex arithmetic coprocessors and their verification
Functional Test for Graphics Controller
High-speed content addressable memory block design
Implementation of the combustion problem main functions based on specialized vector coprocessor FMA operations
Inexact operation prediction scheme realized in multiply-add fused module
Instruction scheduling for vector processors with variable vector length
Leakage Power IC Optimization without RTL Changing
Method and means of built-in self-testing of memory chip
Methodology for creating design-for-test for CMOS VLSI
Methodology of the optimization and efficiency evaluation for the Secondary Cache
Methods of increase of productivity of the superscalar RISC-processor
Microcontroller 1830ÂĹ32Ó – 8-bit MSC-51 architecture in radhard style
Motion Estimation IP-core Implementation for H.264 Full HD Video Codec
Multi-pipelined architecture of high-performance crypto-blocks for using in “Systems on a Chip”
NAND Flash memory controller IP-core
Optical Receiver Architecture for Microprocessor Systems
Optimization of structure of controllers of serial buses. The solution of problems of lack of pins of a integrated circuit and loading of the processor at data transmission
Optimizing the prefetch mechanism in the secondary cache memory
Pipeline Depth Influence on DSP Performance
Placement of Logic Cells of Integrated Circuits with Simultaneous Consideration of Performance and Thermal Mode
Problems of creation of computers of series "Baguet" for problems with increased requirements to reliability of long-term functioning
Processing speed increase and hardware cost reduction in Hsiao decoders
Rank codec IP-core
Readout circuit from the nonvolatile memory
Register file base elements and design flow development for SOI 0.25-micron technology
Research of hardware implementation efficiency of discovering data dependences in coprocessor's pipeline of KOMDIV128-RIO processor
Resonant energy efficiency driver
Route of effective IC development
SATOK - System for Self-Timed Integrated Circuits Testing
SRAM memory controller to maximize switch performance
Schematic-topological design of VLSI cells
Self-Timed Computing Device for High-Reliable Applications
Self-Timed Floating Point Multiply-Add Unit
Set of integrated circuits designed to control power transistor switches
Single Precision Reciprocal and Inverse Square Root Functions Modules
Speed-Independent Fused Multiply-Add Unit of Gigaflops Rating: Implementation Variants
Speed-Independent Fused Multiply-Add Unit of Gigaflops Rating: Methodological Aspects
Standalone verification of microprocessors using reference models with various levels of abstraction
Synthesis external interrupt controller with dynamically change the priority
The Functional Method of the Analysis of Speed-Independent Circuits of Any Size
The block of self-testing of internal memory
The implementation of channels of DDR4 RAM for microprocessor "Elbrus-8Ń2"
The method of timing optimization for FPGA at the microarchitecture level using the pipelining mechanism
The parametric optimization and the automatic tuning for digital state regulators
The technique of test generator realization for built-in self-test circuitries
Use of parallel computing in VLSI computer-aided design
VLSI microprocessor monitoring unit
Variable-length code packing IP-core
Virtualizing IO devices
64-bit superscalar embedded RISC microprocessor

Copyright © 2009-2018 IPPM RAS. All Rights Reserved.

Design of site: IPPM RAS