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Listing of works with the partition by the subject of reports. Click on the work title to see its details. The selected set may be restricted by specifying a range of conference years, or by selecting a specific topic.

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ADC design problems
Cellular automata
Design of System-on-chip (SoC) and IP-blocks
Design of VLSI elements
Design of VLSI signal processors
Design of analog and mixed functional blocks of VLSI
Design of digital functional blocks of VLSI
Design of fault-tolerance systems
Design of micro-electromechanical systems
Design of nanoelectronic devices
Design of nanoelectronic devices based on Josephson junctions
Design of photodetecting VLSI
Design of radiation-resistant VLSI
Design of technological processes
Designing components for aerospace and navigation technology
Genetic algorithms in VLSI CAD
Methods and algorithms for automated layout design
Methods for high-level simulation
Methods of device technology simulation of VLSI
Methods of digital information processing and digital filters
Methods of electro-thermal simulation
Methods of logic synthesis and functional logic simulation ...
Methods of simulation of VLSI electrical characteristics
Models of devices for circuit simulation
Problems of development of sensory microcircuitry
Simulation of data transfer channels
Study of the magnetic properties of materials
Unconventional computing systems
design of memory cells
Selection on topic: Methods and algorithms for automated layout design
Selected papers: from 2005 to 2018 year
In selection - 72 papers
About duplication of elements at VLSI layout
Adaptation in Problems of VLSI Topology Designing
Adaptive procedure of choice of modules orientation at VLSI planning
A global router for nanometer standard cells
Algorithm for Constructing Voronoi Diagram of Orthogonal Polygons in Linf-metric
Algorithm for design rule violation clean-up after physical design
Algorithms for dynamic all-pairs shortest path problem
Algorithms of evolutionary swarm intelligence for solving graph partition problem
Analysis of the impact of standard cells placement and power network configuration on the layout design of a microprocessor component
A physical synthesis to islands of cells with the same diffusion width
Application of dynamic Voronoy diagrams to design rule checking
A stick-diagram based standard cell layout synthesis tool
Automatic Determining of Auxiliary Constraints at Boundaries for Standard Cells Synthesis Flow
Automatic layout synthesis of standard cell layouts based on re-using existing transistor placement patterns and routing patterns
Bioinspired VLSI chip planning methods
Bioinspired VLSI chip planning methods
Choice of optimum connections in a tree in view of Elmore delays
Cognitive Contradictionís Visualization for VLSI Layout Decomposition for Double Patterning Issues
Comparative analysis of the memory elements and sense amplifiers for high-temperature VLSI RAM
Complex algorithm of switch box routing
Computer-aided design of topology of functional blocks of custom digital VLSI
Configuration of microelectronic means on the basis of iterative clusterization taking into account time delays
Constraint Driven VLSI Floorplanning by Non-Linear Optimization
Converting VLSI macroblock structure by regrouping uniform function blocks
DFM Improvement of Hierarchical Layouts
Decomposition Algorithm of the Electronic Circuits with Elements with Varied Area
Design a functional model of FPGA whith single-driver technology in Xilinx ISE system
Determination and comparison of M-factor for devices with the type defined by the user (GENERIC)
Development of algorithm of three-dimensional layout of VLSI on the basis of iterative clusterization
Electromigration Tolerance Improvement in Standard Cells
Evolutionary routing in the channel on the basis of symbolical representations
Flip Chip package design for sophisticated ASIC under small lot production
Gate nets routing in nanometer standard cells with ports placement
Genetic search at construction of connecting trees at a design stage of VLSI layout
Global placement algorithm for structured ASIC
Global routing accounting time restrictions and route-making resources
Heuristics of netless final layout of unrouted nets in the commutational block
IR voltage drop and Electromigration Aware Wire Sizing Algorithm
Improving the efficiency of the design integrated circuits on FPGA with limited resources to trace
Initial placement of digital logic cells in integrated circuits considering net priority
Layout of microelectronic means on the basis of the multilevel approach
MSV-driven VLSI floorplanning
Method of construction of restrictions for an expanded set of technological rules
Method of placement blocks of three dimensional integration IC
Methods of designing custom IP-blocks based on the elements with regular topological structure in layers of polysilicon and diffusion
Minimization of undesired layout patterns during standard cell synthesis
Multi-layer global routing by a method of collective adaptation
Non-linear optimization framework for cell placement legalization
Optimization for some phase of Komdiv64-RIO design flow
Optimization of VLSI Regular Power Grid
Parallel VLSI Layout Decomposition Algorithm for Double Patterning
Placement of Logic Cells of Integrated Circuits with Simultaneous Consideration of Performance and Thermal Mode
Polygons size and form optimization in layout compaction process
Probabilistic approximation of a location problem
Problem of a transistor length variation in a standard cell at multi-objective optimization of nano-size VLSI
Procedures of Channel Rooting on the Basis of Hybridization of Swarm Intelligence with Genetic Search
Results of computer modelling of the decision of a problem of placing of elements VLSI taking into account time delays
Routing of Memory Bits Cells with Automated Construction of Boundary Layout Constraints
Schematic-topological design of VLSI cells
Shortest trees construction on the basis alternatives field crystallization method
Splitting on the basis of multilevel parallel evolutionary adaptation
Standard Cell Routing via Boolean Satisfiability
Synthesis of memory units using a description of design rules via Boolean functions of layout objects
Synthesis of topology of standard CMOS cells taking into account effect of electromigration
System of Compaction and Migration of Standard Cell Layouts
The advanced algorithms of comparison of graphs of electric circuits
The logical elements of comparison for the sub-100 nm CMOS selectors of associative memory
Transistor placement at standard cell level
Two-level evolutional-genetic routing of electric circuits on graph models
Voronoi diagram based graph models building in VLSI physical design
Yield enhancement of standard cell layout

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