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Rozhdestvenskij Yu.V.

Federal Research Center “Computer Science and Control” of the RAS

Listing of all the works of the author. Click on the work title to get the full information.

2006 
 Rozhdestvenskij Yu.V., Morozov N.V., Stepchenkov Yu.A., Rogdestvenskene A.V.
ASIAN - Self-Timed Logic Circuits Analysis Subsystem
2008 
 Diachenko Yu.G., Rozhdestvenskij Yu.V., Morozov N.V., Stepchenkov D.Yu.
Quasi Self-Timed Computing Device: Practical Implementation
2010 
 Stepchenkov Yu.A., Diachenko Yu.G., Rozhdestvenskij Yu.V., Morozov N.V., Stepchenkov D.Yu.
Self-Timed Computing Device for High-Reliable Applications
 Rozhdestvenskij Yu.V., Morozov N.V., Rogdestvenskene A.V.
ASPECT – a Subsystem of Event Analysis of Self-Timed Circuits
2014 
 Sokolov I.A., Stepchenkov Yu.A., Rozhdestvenskij Yu.V., Diachenko Yu.G.
Speed-Independent Fused Multiply-Add Unit of Gigaflops Rating: Methodological Aspects
 Stepchenkov Yu.A., Rozhdestvenskij Yu.V., Diachenko Yu.G., Morozov N.V., Stepchenkov D.Yu., Surkov A.V.
Speed-Independent Fused Multiply-Add Unit of Gigaflops Rating: Implementation Variants
 Bobkov S.G., Gorbunov M.S., Diachenko Yu.G., Rozhdestvenskij Yu.V., Stepchenkov Yu.A., Surkov A.V.
Delay Insensitive Circuits for Low Power and Highly Reliable Microprocessors
2016 
 Stepchenkov Yu.A., Rozhdestvenskij Yu.V., Diachenko Yu.G., Morozov N.V., Stepchenkov D.Yu., Stepanov B.A., Djachenko D.Yu., Rogdestvenskene A.V.
Self-Timed Floating Point Multiply-Add Unit
 

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