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Gavrilov S.V.


Listing of all the works of the author. Click on the work title to get the full information.

 Gavrilov S.V., Glebov A.L.
Noise analysis of digital circuits with accounting of logic constraints
 Solovyev R.A., Gavrilov S.V.
Delay noise analysis, using graph of constraint pairs
 Gavrilov S.V., Glebov A.L., Lyalinskaya O.V., Solovyev R.A.
Application of standard cell characterization results in statistical timing analysis
 Solovyev R.A., Glebov A.L., Gavrilov S.V.
Static timing analysis aware false conduct path detection in terms of logic implication
 Kagramanyan E.R., Gavrilov S.V., Egorov Yu.B.
Standard cell characterezition methodoligy with respect MOSFET threshold voltage variation
 Bragin K.R., Gavrilov S.V., Kagramanyan E.R.
Logic-timing analysis methodology for characterization of custom blocks of digital CMOS IC
 Solovyev R.A., Gavrilov S.V., Glebov A.L.
Statistical timing analysis aware of reconvergence of conduction paths and transition variations
 Gudkova O.N., Gavrilov S.V.
Logical timing analysis of digital IC reliability with NBTI and HCI degradation effects
 Gudkova O.N., Skachkova E.P., Muhanyuk N.N., Gavrilov S.V., Solovyev R.A.
The Methods of Fast Characterization of Large Scale Integration Parameterized IP-blocks
 Gudkova O.N., Gavrilov S.V., Egorov Yu.B.
The Method of Section Approximation for Grid Optimization for Standard Cell Library Characterization
 Gavrilov S.V., Gudkova O.N., Severtsev V.N.
CMOS circuit interval static timing analysis accounting for logic correlations
 Gavrilov S.V., Gudkova O.N., Pirutina G.A.
The Gate Delay Analysis Method Accounting for Simultaneous Input Switching
 Volobuev P.S., Gavrilov S.V., Ryzhova D.I.
The method of static power reducing for CMOS circuits based on sleep transistors with operation speed control
 Gavrilov S.V., Ivanova G.A., Manukyan A.A.
Methods of designing custom IP-blocks based on the elements with regular topological structure in layers of polysilicon and diffusion
 Ryzhova D.I., Gavrilov S.V.
The method of peak current estimation at logic level taking into account simultaneous switching of inputs
 Gavrilov S.V., Zhukova T.D., Ryzhova D.I.
Optimization methods of coding circuits based on the binary decision diagrams for synthesis of fault-tolerant micro- and nanoelectronic circuits
 Gavrilov S.V., Zhukova T.D., Ryzhova D.I.
The methods of time-logic analysis of library elements and VLSI blocks for advanced technologies with a vertical transistorís gate
 Gavrilov S.V., Zheleznikov D.A., Chochaev R., Khvatov V.M.
Partitioning Algorithm Based on Simulated Annealing for Reconfigurable Systems-on-Chip

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