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Stenin V.Ya.

NIISI RAS
National Research Nuclear University "MEPHI"

Listing of all the works of the author. Click on the work title to get the full information.

2005 
 Krasnyuk A.A., Stenin V.Ya.
Simulation of SEU failures in submicronic SoS CMOS cells of memory in view of temperature effects
2006 
 Zharkov I.A., Krasnyuk A.A., Stenin V.Ya.
Reduction of influence of single interference in submicronic trigger memory cells
2008 
 Krasnyuk A.A., Stenin V.Ya., Cherkasov I.G., Yakovlev A.V.
The analysis of operability łą submicronic RAM CMOS VLSI at extreme thermal modes
 Stenin V.Ya., Betelin V.B., Bobkov S.G., Krasnyuk A.A., Osipenko P.N., Cherkasov I.G., Chumakov A.I., Yanenko A.V.
Prospects of using submicronic CMOS VLSI in failure-proof equipment working under impact of atmospheric neutrons
2012 
 Katunin Yu.V., Stenin V.Ya.
The single event transient simulation of the two-phase CMOS inverters for sub-100-nm standards
 Stenin V.Ya., Stepanov P.V.
Single-Event Upset Simulation of the 65 nm 6T CMOS Static Memory Cells
2014 
 Stenin V.Ya., Stepanov P.V.
The DICE cells layout design for the hardened CMOS 28 nm SRAM
 Katunin Yu.V., Stenin V.Ya.
The two-phase 28-nm CMOS inverters in SET-tolerant logics
 Stenin V.Ya.
Simulation of SEU transients in CMOS 28-nm DICE cells subject to single-event multi-node charge collection
2016 
 Stenin V.Ya., Antonyuk A.V.
The logical elements of comparison for the sub-100 nm CMOS selectors of associative memory
 Stenin V.Ya., Katunin Yu.V., Stepanov P.V.
CMOS 65-nm static RAM on DICE cells with spacing groups of transistors
2018 
 Katunin Yu.V., Stenin V.Ya.
Analysis Based on TCAD Simulation of Failure Tolerance of the Elements on the Cells STG DICE for 65-nm CMOS Blocks of Associative Memory
 

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