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Stepchenkov Yu.A.

Federal Research Center “Computer Science and Control” of the RAS

Listing of all the works of the author. Click on the work title to get the full information.

2005 
 Stepchenkov Yu.A., Petrukhin V.S., Diachenko Yu.G.
Experience in Self-Timed Microcontroller Core Design on Basic Gate-Array
2006 
 Stepchenkov Yu.A., Diachenko Yu.G., Grinfeld F.I., Morozov N.V., Plekhanov L.P., Denisov A.N., Filimonenko O.P., Fomin Yu.P.
A Library of Self-Timed Elements or ASIC-Technology
 Petrukhin V.S., Stepchenkov Yu.A., Morozov N.V., Stepchenkov D.Yu.
SATOK - System for Self-Timed Integrated Circuits Testing
 Rozhdestvenskij Yu.V., Morozov N.V., Stepchenkov Yu.A., Rogdestvenskene A.V.
ASIAN - Self-Timed Logic Circuits Analysis Subsystem
2008 
 Stepchenkov Yu.A., Diachenko Yu.G., Bobkov S.G.
Quasi-Delay-Insensitive Computing Device: Methodological and Algorithmic Aspects
2010 
 Stepchenkov Yu.A., Diachenko Yu.G., Rozhdestvenskij Yu.V., Morozov N.V., Stepchenkov D.Yu.
Self-Timed Computing Device for High-Reliable Applications
 Volchek V.N., Stepchenkov Yu.A., Petrukhin V.S., Prokofyev A.A., Zelenov R.A.
Digital Signal Processor With Non-Conventional Recurrent Data-Flow Architecture
2012 
 Shneider A.U., Petrukhin V.S., Stepchenkov Yu.A.
Development Principles of Debugging Tools for Recurrent-Computing Device
2014 
 Bobkov S.G., Gorbunov M.S., Diachenko Yu.G., Rozhdestvenskij Yu.V., Stepchenkov Yu.A., Surkov A.V.
Delay Insensitive Circuits for Low Power and Highly Reliable Microprocessors
 Sokolov I.A., Stepchenkov Yu.A., Rozhdestvenskij Yu.V., Diachenko Yu.G.
Speed-Independent Fused Multiply-Add Unit of Gigaflops Rating: Methodological Aspects
 Stepchenkov Yu.A., Rozhdestvenskij Yu.V., Diachenko Yu.G., Morozov N.V., Stepchenkov D.Yu., Surkov A.V.
Speed-Independent Fused Multiply-Add Unit of Gigaflops Rating: Implementation Variants
2016 
 Stepchenkov Yu.A., Diachenko Yu.G., Khilko D.V., Petrukhin V.S.
Recurrent data-flow architecture: features and realization problems
 Stepchenkov Yu.A., Rozhdestvenskij Yu.V., Diachenko Yu.G., Morozov N.V., Stepchenkov D.Yu., Stepanov B.A., Djachenko D.Yu., Rogdestvenskene A.V.
Self-Timed Floating Point Multiply-Add Unit
 Khilko D.V., Stepchenkov Yu.A., Shikunov D.I., Shikunov Yu.I.
Recurrent data-flow architecture: technical aspects of implementation and modeling results
2018 
 Khilko D.V., Stepchenkov Yu.A., Shikunov Yu.I., Orlov G.A.
Development of Capsule Programming Means for Recurrent Data-flow Architecture
 Sokolov I.A., Rozhdestvenskij Yu.V., Diachenko Yu.G., Stepchenkov Yu.A., Morozov N.V., Stepchenkov D.Yu., Djachenko D.Yu.
Delay-Insensitive Floating Point Multiply-Add-Subtract Unit
 

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