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National Research Nuclear University "MEPHI"

Listing of all the works of the organization. Click on the work title to get the full information.

 Aryashev S.I., Krasnyuk A.A., Chibisov P.A.
Adaptation of performance tests for the 64-bit universal superscalar microprocessor
 Bajkov V.D., Garmash A.A., Samonov A.A., Sevryukov A.N.
Designing PLL-blocks for systems of synchronization of integrated devices of information processing
 Samonov A.A.
Designing of a universal analog kernel of sigma-delta ADC of a sound range
 Dobrovolskij O.A.
Digital kernels of sigma-delta ADC/DAC and technology of their designing
 Zubakov A.V., Kondratenko S.V., Sevryukov A.N.
Experience of designing built-in means and methods of characteristics measurement concerning microelectronic systems
 Bajkov V.D., Gerasimov Yu.M., Rogatkin Yu.B.
Peripheral analog-digital blocks for CMOS VLSI of type "system-on-chip"
 Krasnyuk A.A., Stenin V.Ya.
Simulation of SEU failures in submicronic SoS CMOS cells of memory in view of temperature effects
 Karmazinsky A.N.
To creation of the domestic concept of systems on a crystal
 Shagurin I.I., Rodionov A.A., Belov D.V.
Controller IP-block for control functions realization in SoC
 Shagurin I.I., Shaltyrev V.A.
Creation of "system-on-chip" on the basis of PLIC with use of synthesized processor kernels
 Zharkov I.A., Krasnyuk A.A., Stenin V.Ya.
Reduction of influence of single interference in submicronic trigger memory cells
 Volkov I.N., Goldsher A.I., Dik P.A., Kucherskij V.R., Mashkova V.S.
Set of integrated circuits designed to control power transistor switches
 Davydov G.G., Sogoyan A.V., Petrov A.G., Artamonov A.S., Yashanin I.B., Skobelev A.V., Sedakov A.Yu.
Application of a technique of not destroying control of dose stability of parties SoS CMOS VLSI
 Shagurin I.I., Rodionov A.A., Kanyshev V.O.
Designing SoC on the basis of library of IP-blocks GRLIB of company Gaisler Research
 Gerasimov Yu.M., Glushkov A.V., Grigoryev N.G., Petrichkovich Ya.Ya., Solokhina T.V.
Features of designing of radiation-proof libraries of elements, complex-functional blocks and nano-VLSI SoC
 Shagurin I.I., Shaltyrev V.A.
Methods of optimization of synthesized processor cores at realization of system-on-chp on the basis of FPGA
 Stenin V.Ya., Betelin V.B., Bobkov S.G., Krasnyuk A.A., Osipenko P.N., Cherkasov I.G., Chumakov A.I., Yanenko A.V.
Prospects of using submicronic CMOS VLSI in failure-proof equipment working under impact of atmospheric neutrons
 Chumakov A.I., Pechenkin A.A., Egorov A.N., Mavritskiy O.B., Baranov S.V., Vasilyev A.L., Krinitskij A.V.
SEE sensitive parameters estimation in VLSI using local laser technique
 Krasnyuk A.A., Stenin V.Ya., Cherkasov I.G., Yakovlev A.V.
The analysis of operability ůŕ submicronic RAM CMOS VLSI at extreme thermal modes
 Panteleev A.Yu., Shagurin I.I., Derevyanko D.A.
Applying OpenCL Technology to Vector Processor Design
 Osipov D.L.
Design of behavioral model of sample and hold circuit based on the results of chip testing
 Sogoyan A.V.
Estimation of CMOS VLSI hardness for high dose rate pulse irradiation
 Chumakov A.I.
Estimation of Single Event Effect Sensitivity Parameters by Local Laser Irradiation
 Butuzov V.A., Bocharov Y.I., Gumenyuk A.S., Osipov D.L., Simakov A.B., Atkin E.V.
IP-core of High-Speed Low-Power ADC for multi-channel SoC
 Vorobushkov V.V., Ryabtsev Yu.S.
Methods of power delivery system noise immunity improvement in system on chip “Elbrus-S”
 Bajkov V.D., Gerasimov Yu.M., Kondratenko S.V., Solokhina T.V.
Special features and results of designing the family of LVDS CMOS 0,25/0,18/0,13 ěm drivers and receivers
 Olchev S.I.
Submicron CMOS digital elements with elevated performance stability from the impact of atmospheric neutrons
 Pechenkin A.A., Vasilyev A.L., Kozlov A.A., Koltsov D.O., Orlov A.A., Tararaksin A.S., Chumakov A.I., Yanenko A.V.
Test and Computer Simulation Procedure for Single Event Effect Prediction of ICs in a Space Environment
 Egorov A.N., Mavritskiy O.B., Chumakov A.I., Pechenkin A.A., Koltsov D.O.
Automated Picosecond Laser Facility for Single Event Effects Simulation in Microelectronic Devices under Space Environment
 Chumakov A.I., Vasilyev A.L., Pechenkin A.A., Savchenkov D.V., Tararaksin A.S., Yanenko A.V.
Estimation of ICs SEE Sensitivity Using Local Laser and Pulse Gamma-Ray Technique
 Krasnyuk A.A., Petrov K.A.
Features of application ECC methods in sub-100 nm SRAMs for space systems
 Ulanova A.V., Sogoyan A.V., Chumakov A.I., Nikiforov A.Y., Petrov A.G.
Features of the radiation hardness evaluation for integrated circuits in specialized protective packages
 Gromov D.V., Matveev Y.A., Nazarova G.N.
Impact of ionizing radiation on GaN HEMTs
 Osipov D.L.
Influence of parasitic parameters on the characteristics SAR ADC with switched capacitor DAC
 Panteleev A.Yu.
Instruction scheduling for vector processors with variable vector length
 Tselykovskiy A.A., Danilov I.A., Zebrev G.I.
Modeling of graphene electronics analog devices
 Stenin V.Ya., Stepanov P.V.
Single-Event Upset Simulation of the 65 nm 6T CMOS Static Memory Cells
 Tararaksin A.S., Nigmatullin R.R., Savchenkov D.V., Solovyov S.A., Yanenko A.V.
Single Event Latchup and Catastrophic Failure in CMOS Devices Investigation and Prevention Methods
 Katunin Yu.V., Stenin V.Ya.
The single event transient simulation of the two-phase CMOS inverters for sub-100-nm standards
 Panteleev A.Yu., Shagurin I.I.
Using convertible addressing modes to improve performance of DSP co-processors in a multicore SoC
 Boruzdina A.B., Ulanova A.V., Gorbunov M.S., Chumakov A.I.
Dependence of MCU Sensitivity in SRAM on Data Pattern and angle of incident
 Katunin Yu.V., Levin K.E.
Design of the error-correcting code blocks using the two-phase CMOS logic elements
 Krasnyuk A.A., Orlov O.M., Imametdinov A., Maryina E.
Development and modeling for submicron PDCFET transistors
 Chumakov A.I., Savchenkov D.V., Pechenkin A.A., Mavritskiy O.B., Egorov A.N.
Experimental Verification of Some Laser Techniques' Approximations
 Mavritskiy O.B., Egorov A.N., Pechenkin A.A., Savchenkov D.V., Telets V.A.
Femtosecond Laser System for VLSI Heavy Ion Induced Single Event Effects Hardness Testing
 Gerasimov Yu.M., Domozhakov D.A., Kondratenko S.V., Lomakin S., Solokhina T.V.
Methods of implementation of high-speed serial channels CMOS transceivers on a physical level
 Smolin A.A., Ulanova A.V., Sogoyan A.V., Demidov A.A.
Modeling TID leakage current in MOS-structures under x-ray and gamma irradiation
 Andrianov A.V.
Prototyping linux kernel drivers in userspace with lua scripting language
 Gerasimov Yu.M., Grigoryev N.G., Goussev V.V., Kobylyatskiy A.V., Petrichkovich Ya.Ya.
Radiation-hardned CMOS VLSI SRAM in bulk technology
 Novikov A.A., Pechenkin A.A., Ryasnoy N.V., Chumakov A.I.
SEE sensitivity changes at different TID levels
 Stenin V.Ya.
Simulation of SEU transients in CMOS 28-nm DICE cells subject to single-event multi-node charge collection
 Zebrev G.I., Gorbunov M.S., Useinov R.G., Ozerov A., Emeliyanov V.V., Anashin V.S., Kozukov A., Zemtsov K., Sheredeko G.
Statistical approach to multiple cell upsets description in highly scaled memory circuits
 Usachev N.A., Elesin V.V., Nazarova G.N., Chukov G.V., Telets V.A., Amburkin K.M., Sotskov D.I., Dmitriev V.A., Shelepin N.A.
System approach to design UHF RFID reader transceiver ICs
 Stenin V.Ya., Stepanov P.V.
The DICE cells layout design for the hardened CMOS 28 nm SRAM
 Litvinov E.I., Zhikharev G.Y., Shagurin I.I.
The capabilities of usage virtual platforms for verification of RTL-models of complex co-processor blocks
 Katunin Yu.V., Stenin V.Ya.
The two-phase 28-nm CMOS inverters in SET-tolerant logics
 Bajkov V.D., Garmash A.A., Dubinskiy A.V.
Using the gate capacitance of MOS transistor as LPF's capacitance and its impact on the PLL's characteristics of quality
 Domozhakov D.A., Dubinskiy A.V., Rannev N.Y.
Bit error rate calculation in high performance communication channels
 Shchigorev L.A.
Built-in self-repair for SRAM with redundant elements
 Stenin V.Ya., Katunin Yu.V., Stepanov P.V.
CMOS 65-nm static RAM on DICE cells with spacing groups of transistors
 Kiseleva A.A., Krasnyuk A.A., Trepalin A.P.
Comparative analysis of the memory elements and sense amplifiers for high-temperature VLSI RAM
 Boruzdina A.B., Temirbulatov M.S., Pechenkin A.A., Ulanova A.V., Yashanin I.B., Enns V.I., Yanenko A.V., Chumakov A.I.
Features of experimental research methods for memory with error correction
 Shunkov V.E., Kus O.N., Prokopyev V.Y., Butuzov V.A., Bocharov Y.I., Shunkov V.E.
Fully Integrated Switched-Capacitor DC/DC Converter
 Mushkaev S.V., Andrianov A.V.
Hybrid method of memory allocating in multibank platforms based on the DSP NeuroMatrix architecture
 Chumakov A.I., Sogoyan A.V., Boruzdina A.B., Smolin A.A., Pechenkin A.A.
Mechanisms of Multiple Cell Upsets in Memory
 Shagurin I.I., Zhikharev G.Y.
Multi-pipelined architecture of high-performance crypto-blocks for using in “Systems on a Chip”
 Moskovskaya Y., Sorokoumov G., Bobrovsky D.V., Nikiforov A.Y., Denisov A.N., Snicar V.G., Zhukov A.A., Ulanova A.V.
Rational composition of typical grading system for ASIC’s radiation hardness testing
 Stenin V.Ya., Antonyuk A.V.
The logical elements of comparison for the sub-100 nm CMOS selectors of associative memory
 Gerasimov Yu.M., Grigoryev N.G., Kobylyatskiy A.V.
The technique of logical circuit parameters selection in nanometer RHBD CMOS VLSI
 Chumakov A.I.
Two-Parameter Model for Estimation SEE Sensitivity of VLSI under Ion Irradiation
 Katunin Yu.V., Stenin V.Ya.
Analysis Based on TCAD Simulation of Failure Tolerance of the Elements on the Cells STG DICE for 65-nm CMOS Blocks of Associative Memory
 Galimov A., Gorbunov M.S., Zebrev G.I.
Cross-section Partitioning Technique for Multiple Cell Upsets Rate Simulation in Space Environment
 Andrianov A.V.
Methods of Achieving Test Scenario Portability Between Different Verification Environments
 Chumakov A.I., Bobrovsky D.V., Pechenkin A.A., Savchenkov D.V., Sorokoumov G.
Non-Stable Single Event Latch-up
 Kobylyatskiy A.V., Sergeev D.K.
On-chip Standard Cell Delay Verification Techniques
 Sogoyan A.V., Chumakov A.I., Smolin A.A.
Single Event Rate Evaluation for Modern ICs
 Shchigorev L.A.
Structure and Algorithm Development of Built-in Self-repair for SRAM

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