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Electronic VLSI Engineering & Embedded Systems (ELVEES) R&D Center of Microelectronics

Listing of all the works of the organization. Click on the work title to get the full information.

 Glushkov A.V., Belyaev A.A., Putrya F.M., Alekseev I.N., Mironova Yu.V.
“MULTICORE” platform IP-library of SoC peripherals
 Glushkov A.V., Solokhina T.V., Petrichkovich Ya.Ya.
Alarm controllers MS-0226 and ÌÑ-0226G on the basis of platform "MULTICORE"
 Goussev V.V., Enin S.V., Lihih S.N., Lavlinsky S.A., Menyajlov D.E., Petrichkovich Ya.Ya., Skok D.V., Solokhina T.V., Smirnova I.I., Sudnev E.N., Gerasimov Yu.M.
Analog-digital "system-on-chip" MF01 of series "Multiflex"
 Glushkov A.V., Gribov Yu.I., Silin V.A., Solokhina T.V., Gerasimov Yu.M., Nefedov V.A., Shejnin Yu.E.
Analog-digital "system on crystal" peripheral controller MCT-01 on the basis of IP-libraries of a platform "MULTICORE"
 Solokhina T.V., Petrichkovich Ya.Ya., Glushkov A.V.
Architecture of domestic IC series of type "system or network on chip" on the basis of IP-libraries of platform "MULTICORE"
 Kozlova N.N., Solokhina T.V., Gribov Yu.I., Belyaev A.A.
Configurable IP-cores architecture analysys using criterion of implementation ability in “MULTICORE” platform IP-library
 Aleksandrov Yu.N., Nikolsky V.F., Kuchinsky A.S., Chuprinov A.A., Grachev R.V., Mironova Yu.V.
Library of applied functions in structure of MCStudio™ environment for development of the software "system-on-chip" of series "MULTICORE"
 Belyaev A.A., Solokhina T.V., Glushkov A.V., Aleksandrov Yu.N., Petrichkovich Ya.Ya., Mironova Yu.V., Gerasimov Yu.M.
MCam-01 mixed signal multimedia processor
 Belyaev A.A.
Organization of instruction pipeline in ELcore-õxTM DSP-cores of “MULTICORE” IP-library
 Bajkov V.D., Gerasimov Yu.M., Rogatkin Yu.B.
Peripheral analog-digital blocks for CMOS VLSI of type "system-on-chip"
 Alekseev M.N.
Route of designing "system-on-chip" on the basis of IP-libraries of a platform "MULTICORE"
 Shejnin Yu.E., Suvorova E.A., Rozhdestvenskij D.A., Solokhina T.V., Glushkov A.V., Alekseev I.N., Gerasimov Yu.M.
Route of development and FPGA-verifications of IP-core of controller SpaseWire link for "system-on-chip" on the basis of platform "MultiCore"
 Perekin R.N., Glushkov V.D., Glushkov A.V., Nikolsky V.F.
Technology of debugging "system-on-chip" of series "MULTICORE"
 Sinitsyn V.V., Kosyrev S.A., Nikolsky V.F.
The environment of development of the software for "system-on-chip" of series "MULTICORE" MCStudio_Lnx
 Aleksandrov Yu.N., Kuchinsky A.S., Zinchenko O.N., Kolobanova E.S., Solokhina T.V.
Characteristics of the "Multicore" series controllers for FFT processing signal in real time and their application in radar
 Solokhina T.V., Glushkov A.V., Petrichkovich Ya.Ya., Grishin V.Yu., Eremeev P.M., Sirenko V.G., Shejnin Yu.E.
Family of domestic DSP-controllers "MultiCore" and elements of system interface "MultiCore-the designer" for construction of scaled parallel systems of teraflop productivity
 Glushkov A.V., Solokhina T.V., Petrichkovich Ya.Ya., Gorbachev S.V., Suvorova E.A., Shejnin Yu.E.
Multiprotocol switchboards for the heterogeneous distributed onboard complexes
 Putrya F.M.
Optimization of structure of controllers of serial buses. The solution of problems of lack of pins of a integrated circuit and loading of the processor at data transmission
 Belyaev A.A.
Pipeline structure optimization according to performance criterion for DSP-core with Harvard architecture
 Aleksandrov Yu.N., Grachev R.V., Solokhina T.V.
The block of digital operative processing ùà matrix thermovisual photoreceiver on the basis of the signal microcontroller
 Solokhina T.V.
Architecture of DSP-accelerators on the basis of a platform "MultiCore" for supercomputers of new generation
 Chernyh A.V.
Digital sigma-delta modulator
 Gerasimov Yu.M., Glushkov A.V., Grigoryev N.G., Petrichkovich Ya.Ya., Solokhina T.V.
Features of designing of radiation-proof libraries of elements, complex-functional blocks and nano-VLSI SoC
 Putrya F.M.
Method of automation of process of development of the crossbar for multicore system whith nonuniform memory access
 Belyaev A.A., Gribov Yu.I., Solokhina T.V.
Pipelining and parallelization: two approaches to rise computational performance
 Putrya F.M.
Research, development and optimization of data exchange hardware in multicore computing systems
 Chernyh A.V.
Research and development of structural decisions of frequency synthesizers on the PLL basis
 Yanakova E.S.
The "Multicore" series processors features for signal processing in modern multifunctional radar
 Milov A.N.
The conceptual approach to construction of the device of visualization of three-dimensional images in format OpenGL on processors of a series "Multicore"
 Putrya F.M., Medvedev I.A.
Hardware streams synchronization methods for multicore cluster
 Belyaev I.A.
Huffman encoder IP-core for JPEG image compression
 Yanakova E.S.
Methods of matched filtering radar broadband signals with minimum time delays
 Belyaev A.A.
Pipeline Depth Influence on DSP Performance
 Bajkov V.D., Gerasimov Yu.M., Kondratenko S.V., Solokhina T.V.
Special features and results of designing the family of LVDS CMOS 0,25/0,18/0,13 ìm drivers and receivers
 Medvedev I.A.
An Efficient Router Bufferization for Network-on-Chip Design
 Lobanova A.Y.
Analysis of efficiency of complex use low-power techniques for blocks of digital VLSI
 Belyaev A.A.
Architectural features of VELCore-01 video processing core
 Belyaev I.A.
CAVLC encoder IP-core for H.264/AVC
 Yanakova E.S.
Signal Seepage Impact on the Matched Filtration Results in Radar with Continuous Emission
 Putrya F.M.
SystemVerilog object-oriented programming features for functional verification of multi-core SoC
 Belyaev A.A., Gavrilov V.S., Kuznetsov D.A., Petrichkovich Ya.Ya., Solokhina T.V., Frolov D.S., Funkner A.A.
Evolution in the area of multicore heterogeneous video data processing systems
 Frolov D.S., Pirogov P.P., Aleksandrov Yu.N., Gribov Yu.I., Belyaev A.A.
IP-Core "ACC_Cores" as part system-on-chip. Multifunctional hardware accelerator Fast Fourier Transform - FFT_RT_Core
 Medvedev I.A., Putrya F.M.
Interconnect Verification Methods Based on Unified Test Infrastructure
 Gerasimov Yu.M., Domozhakov D.A., Kondratenko S.V., Lomakin S., Solokhina T.V.
Methods of implementation of high-speed serial channels CMOS transceivers on a physical level
 Belyaev A.A., Kolesnikova I.Y., Kuznetsov D.A.
Motion Estimation IP-core Implementation for H.264 Full HD Video Codec
 Bezglasnaya K.A., Kolbasov Y.S., Medvedev I.A., Putrya F.M.
Problems of platform approach for System on Chip and IP cores test infrastructure creation and their solutions
 Gerasimov Yu.M., Grigoryev N.G., Goussev V.V., Kobylyatskiy A.V., Petrichkovich Ya.Ya.
Radiation-hardned CMOS VLSI SRAM in bulk technology
 Golovina E., Makeeva M., Nikolaev A.V., Putrya F.M., Smirnov A.A.
Reusable complex Soc level tests creating and debugging method
 Bajkov V.D., Garmash A.A., Dubinskiy A.V.
Using the gate capacitance of MOS transistor as LPF's capacitance and its impact on the PLL's characteristics of quality
 Belyaev I.A.
Variable-length code packing IP-core
 Lobanova A.Y., Menshenin L.V.
Analysis of the impact of standard cells placement and power network configuration on the layout design of a microprocessor component
 Zhezlov K.A., Kolbasov Y.S., Kozlov A.O., Nikolaev A.V., Putrya F.M., Frolova S.E.
Automation of verification environments development process providing a through design flow for design, verification and research of IP-blocks and SoC
 Domozhakov D.A., Dubinskiy A.V., Rannev N.Y.
Bit error rate calculation in high performance communication channels
 Gerasimov Yu.M., Grigoryev N.G., Kobylyatskiy A.V.
The technique of logical circuit parameters selection in nanometer RHBD CMOS VLSI

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