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United Institute of Informatics Problems

Listing of all the works of the organization. Click on the work title to get the full information.

2006 
 Bibilo P.N., Kochanov D.A.
Optimizational transformations of VHDL-models of digital systems
 Bibilo P.N., Kardash S.N., Romanov V.I.
SsVER - system of synthesis and verification of combinational logic schemes
2008 
 Bibilo P.N., Audzeyeu M.A.
Designing of regular circuits with consecutive connections of transistors
 Kirienko N.A.
The subsystem for processing structure-functional descriptions of circuits in a CAD system
2010 
 Romanov V.I., Bibilo P.N., Loginova I.P., Cheremisinova L.D.
Computer-aided design of topology of functional blocks of custom digital VLSI
 Bibilo P.N.
Decomposition of Boolean Functions for BDD
 Cheremisinova L.D., Cheremisinov D.I.
Low Power Driven Optimization of Two-Level Logic Circuits
2012 
 Audzeyeu M.A., Zaitsay V.S.
Design criteria of Frequency selection for the internal oscillator UHF RFID tags
 Bibilo P.N., Cheremisinova L.D., Kardash S.N., Kirienko N.A., Leonchik P.V., Novokov D.Ya., Romanov V.I., Cheremisinov D.I.
Low-Power Synthesis of Logical CMOS Circuits
 Bibilo P.N., Soloviev A.L.
VHDL-Simulation-Based Evaluation of CMOS-Circuits Power Consumption
2014 
 Bibilo P.N.
Decomposition and Minimization of Binary Decision Diagrams for Systems of Specified Boolean Functions
 Cheremisinov D.I.
FPGA reverse engineering by model-driven development
 Cheremisinova L.D.
Verification of Logical Descriptions of Combinational Circuits
2016 
 Bibilo P.N.
The use of VHDL models of partial Boolean functions for the design of digital circuits
 Cheremisinov D.I., Cheremisinova L.D.
Use of parallel computing in VLSI computer-aided design
2018 
 Audzeyeu M.A., Bibilo P.N.
Algorithmic Design of Digital Operational Units with Low Power Consumption
 Cheremisinov D.I., Cheremisinova L.D.
Decompilation of Flat CMOS Circuits in SPICE Format
 

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