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Cadence Design Systems

Listing of all the works of the organization. Click on the work title to get the full information.

2005 
 Ivanov A.A., Spitsyn V.Yu., Tian M.
Analog simulation tools and their role in modern designing integrated circuits
 Potyagalova A.S., Soltan I.E., Tkachev D.F., Khapaev M.M.
Experience of application of a reduction of parasitic elements with use of subspace Krylov methods
 Bezrukov A.E., Rusakov A.S., Tkachev D.F., Khapaev M.M.
Methods of the parasitic extraction of interconnect in the integral circuits
 Datsuk A.M., Marchuk V.I.
The advanced algorithms of comparison of graphs of electric circuits
2006 
 Khapaev M.M.
Calculation 2D inductance for extraction problems
 Datsuk A.M., Tsvetkov A.V.
Determination and comparison of M-factor for devices with the type defined by the user (GENERIC)
 Sukharev S.A., Spitsyn V.Yu., Yusim I.E.
Modern tools of compilation of device models from high level language Verilog-A to internal representation of system Spectre
 Bojko A.Ya., Bezrukov A.E., Rusakov A.S., Tkachev D.F., Khapaev M.M.
New Algorithm for the 2D Capacitance calculation in the interconnect parasitic extraction problem
2008 
 Rusakov A.S., Khapaev M.M.
Accuracy Improvement of the Interconnect Parasitic Capacitance Extraction
 Khapaev M.M., Kupriyanov M.Yu.
Calculation of inductance in problems of designing superconductive microelectronic structures
 Potyagalova A.S., Nechepurenko Yu.M.
The general properties and modifications of reduction algorithms
 

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