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NIISI RAS

Listing of all the works of the organization. Click on the work title to get the full information.

2005 
 Aryashev S.I., Krasnyuk A.A., Chibisov P.A.
Adaptation of performance tests for the 64-bit universal superscalar microprocessor
 Aryashev S.I., Nikolina N.V., Chibisov P.A.
Architecture validation tests for RTL-model of 64-bit superscalar microprocessor
 Aryashev S.I., Zubkovskiy P.S., Nikolina N.V., Chibisov P.A.
Common approaches to the FPU verification
 Balashov A.G., Krupkina T.Yu., Tsimbalov A.S.
Criteria of a choice of models at calculation of device characteristics of submicronic transistor structures
 Aryashev S.I., Kornilenko A.V., Chekunov A.V.
Debugging and testing of VLSI models with use of the prototypes realized on PLIC
 Aryashev S.I., Rogatkin B.Yu., Sysoeva O.V.
Debugging of the block of transformation of addresses of the microprocessor
 Bobkov S.G., Tokarev V.E.
Designing of custom-made blocks taking into account extraction RC parasitic parameters
 Rogatkin Yu.B.
Experience of development and methodology of designing mixed MES on an example high-speed 10-digit ADC
 Aryashev S.I., Barskikh M.E., Bychkov K.S.
Methods of increase of productivity of the superscalar RISC-processor
 Bajkov V.D., Gerasimov Yu.M., Rogatkin Yu.B.
Peripheral analog-digital blocks for CMOS VLSI of type "system-on-chip"
 Bobkov S.G.
Problems of creation of computers of series "Baguet" for problems with increased requirements to reliability of long-term functioning
 Antonov S.V., Aryashev S.I.
Route of effective IC development
 Arakelov A.A., Sidorov E.A., Bobkov S.G.
SRAM memory controller to maximize switch performance
 Krasnyuk A.A., Stenin V.Ya.
Simulation of SEU failures in submicronic SoS CMOS cells of memory in view of temperature effects
 Bobkov S.G., Evlampiev B.E., Sidorov A.Yu.
The block of self-testing of internal memory
2006 
 Aryashev S.I., Bobkov S.G., Zubkovskiy P.S.
64-bit superscalar embedded RISC microprocessor
 Zharkov I.A., Krasnyuk A.A., Stenin V.Ya.
Reduction of influence of single interference in submicronic trigger memory cells
2008 
 Stenin V.Ya., Betelin V.B., Bobkov S.G., Krasnyuk A.A., Osipenko P.N., Cherkasov I.G., Chumakov A.I., Yanenko A.V.
Prospects of using submicronic CMOS VLSI in failure-proof equipment working under impact of atmospheric neutrons
 Stepchenkov Yu.A., Diachenko Yu.G., Bobkov S.G.
Quasi-Delay-Insensitive Computing Device: Methodological and Algorithmic Aspects
 Krasnyuk A.A., Stenin V.Ya., Cherkasov I.G., Yakovlev A.V.
The analysis of operability ýŗ submicronic RAM CMOS VLSI at extreme thermal modes
2010 
 Zubkovskiy P.S., Ivasyuk E.V., Aryashev S.I.
Complex arithmetic coprocessor
 Slepov A.B.
Development of behavioural cycle-accurate model of a system-on-chip with C++
 Nikolina N.V., Zubkovskiy P.S., Chibisov P.A.
Floating point and complex arithmetic coprocessors and their verification
 Slinkin D.I., Gruzinova E.V.
Functional Test for Graphics Controller
 Butuzov V.A., Bocharov Y.I., Gumenyuk A.S., Osipov D.L., Simakov A.B., Atkin E.V.
IP-core of High-Speed Low-Power ADC for multi-channel SoC
 Chibisov P.A., Trubitsyn D.A., Baranov S.V.
Memory testing algorithms for microprocessor board radiation test
 Agafonov A.E.
Optical Receiver Architecture for Microprocessor Systems
 Evlampiev B.E., Vlasov A.O., Kirichenko P.G., Kochnov A.A.
Optimization for some phase of Komdiv64-RIO design flow
 Tema A.V., Beloborodova S.V.
Research of hardware implementation efficiency of discovering data dependences in coprocessor's pipeline of KOMDIV128-RIO processor
 Ivasyuk E.V., Zubkovskiy P.S.
Single Precision Reciprocal and Inverse Square Root Functions Modules
 Arakelov A.A., Aryashev S.I., Kabirov R.Sh.
Virtualizing IO devices
2012 
 Petrov K.A.
Error control coding for submicron dynamic RAM
 Krasnyuk A.A., Petrov K.A.
Features of application ECC methods in sub-100 nm SRAMs for space systems
 Rogatkin Yu.B.
IP-block of the digital-to-analog converter with autocalibration
 Zubkovskiy P.S., Ivasyuk E.V.
Inexact operation prediction scheme realized in multiply-add fused module
 Vlasov A.O.
Leakage Power IC Optimization without RTL Changing
 Ladnushkin M.S.
Methodology for creating design-for-test for CMOS VLSI
 Tselykovskiy A.A., Danilov I.A., Zebrev G.I.
Modeling of graphene electronics analog devices
 Nikolina N.V., Chibisov P.A., Aryashev S.I.
Modern trends in evaluating and monitoring of microprocessor performance at the design stage
 Pominova A.A.
Optimization of VLSI Regular Power Grid
 Vlasov A.O., Evlampiev B.E., Kirichenko P.G., Kochnov A.A., Pominova A.A.
Phisical Design Flow optimization for Komdiv64-RIO processor
 Buyakova O.N., Kirichenko P.G., Osina S.E., Sysoeva O.V., Tarasov I.V.
Register file base elements and design flow development for SOI 0.25-micron technology
 Rovinsky E.V., Chibisov P.A.
Running OS Linux as a stage of functional testing of microprocessors
 Stenin V.Ya., Stepanov P.V.
Single-Event Upset Simulation of the 65 nm 6T CMOS Static Memory Cells
 Katunin Yu.V., Stenin V.Ya.
The single event transient simulation of the two-phase CMOS inverters for sub-100-nm standards
2014 
 Vlasov A.O., Evlampiev B.E.
Clock Tree Synthesis Optimization
 Bobkov S.G., Gorbunov M.S., Diachenko Yu.G., Rozhdestvenskij Yu.V., Stepchenkov Yu.A., Surkov A.V.
Delay Insensitive Circuits for Low Power and Highly Reliable Microprocessors
 Boruzdina A.B., Ulanova A.V., Gorbunov M.S., Chumakov A.I.
Dependence of MCU Sensitivity in SRAM on Data Pattern and angle of incident
 Katunin Yu.V., Levin K.E.
Design of the error-correcting code blocks using the two-phase CMOS logic elements
 Krasnyuk A.A., Orlov O.M., Imametdinov A., Maryina E.
Development and modeling for submicron PDCFET transistors
 Aryashev S.I., Barskikh M.E., Bobkov S.G., Zubkovskiy P.S., Ivasyuk E.V.
Implementation of the combustion problem main functions based on specialized vector coprocessor FMA operations
 Aryashev S.I., Bobkov S.G., Sayapin P.V.
Methodology of the optimization and efficiency evaluation for the Secondary Cache
 Barskikh M.E., Aryashev S.I., Rogatkin B.Yu.
Modern methods of functional verification RTL-models blocks for VLSI microprocessor
 Khisambeev I.Sh., Chibisov P.A.
On one method of defining functional coverage metrics for microprocessor testing
 Petrov K.A.
Processing speed increase and hardware cost reduction in Hsiao decoders
 Larionov A.V.
Pseudo-differential cascode output buffer for high-speed serial data transmission across a channel with high losses
 Stenin V.Ya.
Simulation of SEU transients in CMOS 28-nm DICE cells subject to single-event multi-node charge collection
 Stepchenkov Yu.A., Rozhdestvenskij Yu.V., Diachenko Yu.G., Morozov N.V., Stepchenkov D.Yu., Surkov A.V.
Speed-Independent Fused Multiply-Add Unit of Gigaflops Rating: Implementation Variants
 Sysoeva O.V., Agafonov A.E., Kirichenko P.G.
Spread spectrum clock generator design methods
 Zebrev G.I., Gorbunov M.S., Useinov R.G., Ozerov A., Emeliyanov V.V., Anashin V.S., Kozukov A., Zemtsov K., Sheredeko G.
Statistical approach to multiple cell upsets description in highly scaled memory circuits
 Stenin V.Ya., Stepanov P.V.
The DICE cells layout design for the hardened CMOS 28 nm SRAM
 Katunin Yu.V., Stenin V.Ya.
The two-phase 28-nm CMOS inverters in SET-tolerant logics
 Ladnushkin M.S.
Universal scan based JTAG compatible VLSI debug structure
 Rogatkin Yu.B., Rogatkin B.Yu.
VLSI microprocessor monitoring unit
2016 
 Vlasov A.O.
28nm ICís Parameters Optimization without RTL Changing
 Slinkin D.I., Zubkovskiy P.S.
Analysis of modern microprocessors peak performance
 Stenin V.Ya., Katunin Yu.V., Stepanov P.V.
CMOS 65-nm static RAM on DICE cells with spacing groups of transistors
 Kiseleva A.A., Krasnyuk A.A., Trepalin A.P.
Comparative analysis of the memory elements and sense amplifiers for high-temperature VLSI RAM
 Kornilenko A.V., Esula O.I.
Computer memory subsystem optimization by providing guaranteed memory bandwidth
 Larionov A.V.
Decision-feedback equalizer with active inductor for high-speed receiver
 Kirichenko P.G., Solovyeva L.A., Tarasov I.V.
Design of Power Efficient 14-port Register File and Translation Lookaside Buffer in 28-nm Process
 Vlasov A.O., Marakhovsky V.B., Surkov A.V.
Design of digital CMOS circuits for extreme temperatures
 Solovyeva L.A.
Design of the hybrid CAM register
 Kosarev I.
Distributed multi lane serial links for multiprocessor systems interconnects
 Shunkov V.E., Kus O.N., Prokopyev V.Y., Butuzov V.A., Bocharov Y.I., Shunkov V.E.
Fully Integrated Switched-Capacitor DC/DC Converter
 Grevtsev N.A., Khisambeev I.Sh., Chibisov P.A.
Methods to improve efficiency of microprocessor model stochastic tests
 Aryashev S.I., Bychkov K.S.
Optimizing the prefetch mechanism in the secondary cache memory
 Ladnushkin M.S.
Reducing area and increasing compression ratio of scan compression system for digital VLSI using stuck-at fault model
 Barskikh M.E.
Research ways to design a dynamic branch prediction unit for promising microprocessor development by SRISA RAS
 Lavrinov G.A.
Route reconfiguration in RapidIO system in case of faulty connections
 Stenin V.Ya., Antonyuk A.V.
The logical elements of comparison for the sub-100 nm CMOS selectors of associative memory
2018 
 Larionov A.V., Buyakova O.N., Sysoeva O.V., Osina S.E., Zadiabin S.O., Aleksan P.A., Tarasov I.V., Rogatkin Yu.B., Masterov V.
A 4-channel Multi-standard Adaptive Serial Transceiver for the Range 1.25-10.3Gb/s in CMOS 65nm
 Grevtsev N.A., Chibisov P.A.
A Practical Approach to Verification of Multicore Microprocessor Models
 Katunin Yu.V., Stenin V.Ya.
Analysis Based on TCAD Simulation of Failure Tolerance of the Elements on the Cells STG DICE for 65-nm CMOS Blocks of Associative Memory
 Antonyuk A.V., Stepanov P.V.
Analysis of Power Consumption of Matching Signals Summation Circuits for 65 nm CMOS Associative Memory Registers
 Galimov A., Gorbunov M.S., Zebrev G.I.
Cross-section Partitioning Technique for Multiple Cell Upsets Rate Simulation in Space Environment
 Vlasov A.O., Gorelov A.A., Emin E.K.
Optimization of TSMC 28nm Physical and Logical VLSI Design Flow
 Glushko A.A., Babkin S.I., Amirkhanov A.V., Zinchenko L.A., Makarchuk V.V.
Problems of Designing LDMOS-transistors Working at Increased Supply Voltage
 Smirnov A.V., Chibisov P.A.
Random Test Generator for Multicore Microprocessor Cache Coherence Verification (Ristretto)
 Ladnushkin M.S.
Register Duplication for Scan Compression Designs
 Slinkin D.I.
Testing the Performance of the Embedded Gigabit Ethernet Controllerís FPGA Prototype when working with TCP
 Aryashev S.I., Zubkovskiy P.S., Tsvetkov V.V.
The Results of the Implementation of the Copy Function on a Vector Coprocessor
 Barskikh M.E., Esula O.I.
Verification of Memory Requests Arbitration Algorithm
 

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