Home         Authors   Papers   Year of conference   Themes   Organizations        To MES conference

Architecture of fault-resistant FPGA with capacity over 100 thousand gates

Authors
 Tsybin S.A.
 Bystritskij A.V.
 Skuratovich S.N.
Date of publication
 2006

Abstract
 Architectural features of creation fault-resistant high capacity FPGA are considered, the analysis of influence of volume of configuration memory on reliability of a product is carried out, methods of decreasing of configuration memory size for FPGA of given capacity are shown. Approaches are considered which allow to increase
firmness of configuration memory to the single
failures, methods of protection of memory control, and also system methods of control of a state of configuration memory.
Keywords
 fault-resistant FPGA
Library reference
 Tsybin S.A., Bystritskij A.V., Skuratovich S.N. Architecture of fault-resistant FPGA with capacity over 100 thousand gates // Problems of Perspective Microelectronic Systems Development - 2006. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2006. P. 376-381.
URL of paper
 http://www.mes-conference.ru/data/year2006/68.pdf

Copyright © 2009-2019 IPPM RAS. All Rights Reserved.

Design of site: IPPM RAS