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Logic-timing analysis methodology for characterization of custom blocks of digital CMOS IC

Authors
 Bragin K.R.
 Gavrilov S.V.
 Kagramanyan E.R.
Date of publication
 2008

Abstract
 The circuit hierarchical transistor level structure for logic-timing analysis of custom IC block is proposed. It is based on SP-DAG-graph. Estimation of capacitance and conductance and timing analysis are performed in terms of introduced model.
Algorithm is based on branch and bounds method and gives opportunity of delay analysis for quantity of different input signal combination without electrical simulation with exhaustive search of input signal sets.
Keywords
 logic-timing analysis, digital IC, SP-DAG-graph, branch and bounds method
Library reference
 Bragin K.R., Gavrilov S.V., Kagramanyan E.R. Logic-timing analysis methodology for characterization of custom blocks of digital CMOS IC // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2008. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2008. P. 92-97.
URL of paper
 http://www.mes-conference.ru/data/year2008/13.pdf

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