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Pipelining and parallelization: two approaches to rise computational performance

Authors
 Belyaev A.A.
 Gribov Yu.I.
 Solokhina T.V.
Date of publication
 2008

Abstract
 Two approaches to increase performance of digital computational units on microarchitectural level are discussed - pipelining and parallelization. Effectiveness of these two approaches is comparatively analyzed for computational units implemented as the parts of system on the chip.
Keywords
 digital signal processing, system on chip, computational performance, pipelining, parallelization
Library reference
 Belyaev A.A., Gribov Yu.I., Solokhina T.V. Pipelining and parallelization: two approaches to rise computational performance // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2008. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2008. P. 411-414.
URL of paper
 http://www.mes-conference.ru/data/year2008/77.pdf

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