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Quasi-Delay-Insensitive Computing Device: Methodological and Algorithmic Aspects

Authors
 Stepchenkov Yu.A.
 Diachenko Yu.G.
 Bobkov S.G.
Date of publication
 2008

Abstract
 The approaches to self-timed hardware design are presented. The conditions of intersystem integration of synchronous and self-timed devices are considered through the example of the quasi-delay-insensitive computing device development. This device performs functions of division and square root extraction. It operates with numbers of single and double precisions corresponding to the IEEE 754 standard.
Keywords
 Self-timed; quasi-delay-insensitive; division; square root; Radix-2
Library reference
 Stepchenkov Yu.A., Diachenko Yu.G., Bobkov S.G. Quasi-Delay-Insensitive Computing Device: Methodological and Algorithmic Aspects // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2008. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2008. P. 441-446.
URL of paper
 http://www.mes-conference.ru/data/year2008/82.pdf

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