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Design of behavioral model of sample and hold circuit based on the results of chip testing

Authors
 Osipov D.L.
Date of publication
 2010

Abstract
 This paper presents a method for design of a compact behavioral modeling of analog and mixed-signal circuits using Verilog-A based on results of chip testing. To illustrate the proposed method, the process of characterization and testing of the IP-core of SHA, fabricated in UMC 0.18 CMOS process, is described.
Keywords
 model, Verilog-A, IP-core, SHA
Library reference
 Osipov D.L. Design of behavioral model of sample and hold circuit based on the results of chip testing // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2010. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2010. P. 150-153.
URL of paper
 http://www.mes-conference.ru/data/year2010/papers/m10-39-95341.pdf

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