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Optical Receiver Architecture for Microprocessor Systems

Authors
 Agafonov A.E.
Date of publication
 2010

Abstract
 This paper presents an optical receiver architecture for microprocessor systems for
1-Gb/s Ethernet and 1.25-Gb/s RapidIO PON systems using point-to-point topology. Optical receiver
consists transimpedance amplifier (TIA) with automatic gain control (AGC), six limiting amplifiers (LA), signal detect circuit (SDC) and output buffer circuit. The optical receiver demonstrates 59-dBOHm transimpedance gain, 625-MHz bandwidth for a full range of working temperatures. Fabricated in 0.35-m CMOS technology, optical receiver operate with a 3.3-V supply and the power dissipation is 345mW.
Keywords
 optical receiver, amplifier with automatic gain control
Library reference
 Agafonov A.E. Optical Receiver Architecture for Microprocessor Systems // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2010. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2010. P. 438-441.
URL of paper
 http://www.mes-conference.ru/data/year2010/papers/m10-141-94741.pdf

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