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High-frequency low-noise CMOS amplifier

Authors
 Balashov E.V.
 Korotkov A.S.
Date of publication
 2010

Abstract
  method of the parametric synthesis for high-frequency low-noise CMOS amplifiers with low power consumption for communication system frontend is proposed. Synthesized narrow-
band amplifier chip is designed using 0.18-um CMOS UMC technology with operating frequency
2.4 GHz and 4 mW power consumption. The parameters |S21| and |S11| are 22 dB and minus
30 dB, respectively, with noise figure 2.9 dB. The analysis of nonlinear intermodulation distortion using the Volterra series is developed. An estimation accuracy of the intercept point of 3-rd oder IIP3 is 3 dBm. The developed amplifier provides two times lower power consumption compared with similar implementations. The results of simulation and experiment is presented.
Keywords
 CMOS technology, low noise amplifier, moderate inversion, nonlinear distortion, the intercept point of 3-rd order
Library reference
 Balashov E.V., Korotkov A.S. High-frequency low-noise CMOS amplifier // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2010. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2010. P. 565-570.
URL of paper
 http://www.mes-conference.ru/data/year2010/papers/m10-344-79321.pdf

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