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Low-Power Synthesis of Logical CMOS Circuits

 Bibilo P.N.
 Cheremisinova L.D.
 Kardash S.N.
 Kirienko N.A.
 Leonchik P.V.
 Novokov D.Ya.
 Romanov V.I.
 Cheremisinov D.I.
Date of publication

 The structure and the functionality of the software system for energy-saving logical synthesis (ELS) is described. The system is intended for cell library design automation of very large-scale integration (VLSI) CMOS circuits. The high-level languages VHDL and SF are used as source languages for functional description of networks under design. The complexity and power consumption are accepted as optimality criteria when designing CMOS circuits.
 Design automation, custom CMOS VLSI, low-power synthesis
Library reference
 Bibilo P.N., Cheremisinova L.D., Kardash S.N., Kirienko N.A., Leonchik P.V., Novokov D.Ya., Romanov V.I., Cheremisinov D.I. Low-Power Synthesis of Logical CMOS Circuits // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2012. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2012. P. 73-78.
URL of paper

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