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Nanometer merged MOS devices modeling

Authors
 Rakitin V.V.
Date of publication
 2012

Abstract
 This article considers a new type of nanometer-sized devices with a merged MOS transistor (MMOS).
The design and mode are described. The simulation MMOS with minimal topological size of 10 nm is performed. The simulation results show that the simplest MMOS operated at supply voltage of 0.6 V and below, has a voltage gain higher than 10, is functional gigahertz range. It is demonstrated ability to perform on MMOS complex logic functions.
Keywords
 the MOSFET, MMOS transistor, logic gate, modeling.
Library reference
 Rakitin V.V. Nanometer merged MOS devices modeling // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2012. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2012. P. 193-198.
URL of paper
 http://www.mes-conference.ru/data/year2012/pdf/D23.pdf

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