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Single-Event Upset Simulation of the 65 nm 6T CMOS Static Memory Cells

Authors
 Stenin V.Ya.
 Stepanov P.V.
Date of publication
 2012

Abstract
 The memory cell sensitivity characteristics with different width of transistors for the design standard of 65 nm were determined. The impact of individual nuclear particles was simulated by the local current pulse with the rise time constant of 10 ps and fall time constant of 30 ps. Limits of the critical amplitude of the local current pulses amplitudes and the critical charges for 6T CMOS memory cells in the recording, storing and reading modes were estimated.
Keywords
 CMOS memory cell; local current pulse; critical pulse amplitude; critical charge
Library reference
 Stenin V.Ya., Stepanov P.V. Single-Event Upset Simulation of the 65 nm 6T CMOS Static Memory Cells // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2012. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2012. P. 419-422.
URL of paper
 http://www.mes-conference.ru/data/year2012/pdf/D34.pdf

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