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A parallel critical path algorithm with loop detection for static timing analysis of sequential circuits

Authors
 Knyazev N.A.
 Malinauskas K.K.
Date of publication
 2012

Abstract
 Critical path search is one of the key processes in digital circuit timing analysis and verification. For VLSI designs with millions of transistors static timing analysis runtime may exceed 24 hours that essentially complicates the circuit design. In this work we present a parallel algorithm for multi-core computers speeding up the critical path search by an order of magnitude. It supports sequential circuits and critical loop detection thus extending our previously published parallel algorithm for combinational circuits. Asynchronous parallelization approach is used in order to get better processor load balancing. We reached up to 8.9x speedup at 16 processor cores.
Keywords
 parallel algorithm, critical path search, static timing analysis
Library reference
 Knyazev N.A., Malinauskas K.K. A parallel critical path algorithm with loop detection for static timing analysis of sequential circuits // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2012. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2012. P. 43-48.
URL of paper
 http://www.mes-conference.ru/data/year2012/pdf/D147.pdf

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