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Simulation of SEU transients in CMOS 28-nm DICE cells subject to single-event multi-node charge collection

Authors
 Stenin V.Ya.
Date of publication
 2014

Abstract
 The technology node scaling leads to single event upset by a charge sharing in the CMOS SRAM DICE cells during a single event. The DICE cell layouts base on the spacing the two transistor clusters which of them consists of the closed pair N-PMOS transistors and the opened pair N-PMOS transistors. The upset non steady state mechanisms in 28 nm CMOS DICE cell are detailed. The DICE cell single event transients are described.
Keywords
 CMOS DICE cell, single nuclear particle, single-event upset, single event charge sharing, simulation
Library reference
 Stenin V.Ya. Simulation of SEU transients in CMOS 28-nm DICE cells subject to single-event multi-node charge collection // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2014. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2014. Part 3. P. 137-140.
URL of paper
 http://www.mes-conference.ru/data/year2014/pdf/D011.pdf

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