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The DICE cells layout design for the hardened CMOS 28 nm SRAM

Authors
 Stenin V.Ya.
 Stepanov P.V.
Date of publication
 2014

Abstract
 The hardened DICE cells consist of two CMOS transistor clusters. The farther this two CMOS transistor clusters can be placed apart, the more robust the hardened DICE SRAM will be to SEUs. Three versions of DICE CMOS 28 nm SRAM block composition was suggested with 1 μm, 2 μm and 3 μm minimum cluster distance.
Keywords
 CMOS DICE cell, single nuclear particle, layout design, SRAM, simulation
Library reference
 Stenin V.Ya., Stepanov P.V. The DICE cells layout design for the hardened CMOS 28 nm SRAM // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2014. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2014. Part 3. P. 163-166.
URL of paper
 http://www.mes-conference.ru/data/year2014/pdf/D014.pdf

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