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A 8-bit flash ADC with reduced DNL

 Budanov D.O.
 Pilipko M.M.
 Morozov D.V.
Date of publication

 A 8-bit flash ADC designed in 180 nm CMOS is presented. An array of redundant comparators is used for reducing DNL. Simulation and experimental results are discused. ADC's power consumtion is 93 mW, ENOB is 5.8 bit, DNL is 0.23 bit.
 Analog-to-digital converter, comparator, thermometric code, encoder, DNL, INL, ENOB.
Library reference
 Budanov D.O., Pilipko M.M., Morozov D.V. A 8-bit flash ADC with reduced DNL // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2014. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2014. Part 3. P. 35-38.
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