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Clock Tree Synthesis Optimization

 Vlasov A.O.
 Evlampiev B.E.
Date of publication

 On the example of the design process of the CPU core, used in the new VLSI from the family "KOMDIV" (SRISA RAS), clock tree synthesis approaches to speed-up design timing parameters are considered
 clock tree synthesis, multi-Vth standard cell libraries
Library reference
 Vlasov A.O., Evlampiev B.E. Clock Tree Synthesis Optimization // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2014. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2014. Part 4. P. 71-74.
URL of paper

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