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Transistor placement at standard cell level

Authors
 Sorokin A.A.
 Ryzhenko N.V.
Date of publication
 2014

Abstract
 In this paper we present an algorithm of transistor placement within standard cells. The algorithm is based on enumeration of possible partial placements using a weighted cost function. Partial placements are ordered in a horizontal direction and sorted according to the cost function. The cost function is calculated dynamically. It allows routability estimation without construction of a complete placement. Unfeasible and weak intermediate solutions are eliminated from the consideration. Good intermediate solutions are used for the next intermediate placements until all transistors are placed. The algorithm demonstrated applicability for a wide class of standards cells. The algorithm is used for the industrial standard cell synthesis.
Keywords
 placement, standard cells, cell library
Library reference
 Sorokin A.A., Ryzhenko N.V. Transistor placement at standard cell level // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2014. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2014. Part1. P. 133-136.
URL of paper
 http://www.mes-conference.ru/data/year2014/pdf/D040.pdf

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