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FPGA reverse engineering by model-driven development

 Cheremisinov D.I.
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 The problem of converting of the digital system realized on FPGA Spartan 3, into VHDL-descriptions suitable for synthesis of ASIC is considered. The program for the decision of this problem is constructed as the automation tools of the model-driven development.
 FPGA, ASIC, reverse engineering, graph rewriting and transformations.
Library reference
 Cheremisinov D.I. FPGA reverse engineering by model-driven development // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2014. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2014. Part 1. P. 25-30.
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