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Parallel VLSI Layout Decomposition Algorithm for Double Patterning

Authors
 Shakhnov V.A.
 Zinchenko L.A.
 Verstov V.A.
Date of publication
 2014

Abstract
 In the paper VLSI layout including non-Manhattan geometry decomposition approach for the double patterning lithography on high performance computing platforms are discussed. Parallel algorithm for layout decomposition for double patterning are discussed.
Keywords
 VLSI, Double Patterning, Layout Decomposition, Parallel Algorithm
Library reference
 Shakhnov V.A., Zinchenko L.A., Verstov V.A. Parallel VLSI Layout Decomposition Algorithm for Double Patterning // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2014. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2014. Part 1. P. 137-142.
URL of paper
 http://www.mes-conference.ru/data/year2014/pdf/D072.pdf

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