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Recognition and interpretation of erroneous behavior in simulation-based hardware verification

Authors
 Chupilko M.M.
 Protsenko A.S.
Date of publication
 2014

Abstract
 Simulation-based verification is intended for runtime checking of correspondence between HDL-model behavior and its specification. To present specification in necessary form and ensure the correctness checking is possible in different ways, but usually erroneous behavior having been found only establishes the fact of erroneous data on HDL-model outputs. Proposed in this paper approach is aimed not only to find incorrect HDL-model behavior but also to interpret the received output data by means of special algorithm using a set of data analysis rules.
Keywords
 trace analysis, simulation-based verification
Library reference
 Chupilko M.M., Protsenko A.S. Recognition and interpretation of erroneous behavior in simulation-based hardware verification // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2014. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2014. Part 2. P. 91-96.
URL of paper
 http://www.mes-conference.ru/data/year2014/pdf/D100.pdf

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