Home         Authors   Papers   Year of conference   Themes   Organizations        To MES conference

NAND Flash memory controller IP-core

 Rutkevich A.V.
 Polyakov E.A.
 Sysoev I.Y.
Date of publication

 This paper discusses design and architecture of high-speed 4 channel NAND Flash controller ip-core for space and industrial applications. The article includes information on structure, logic utilization and performance evaluation of designed ip-core in modern FPGAs and 180 nm ASICs. As a result a series of PCI-compatible FPGA-based mass-storage devices were produced.
 controller, memory, FPGA, ASIC, IP-core, NAND Flash
Library reference
 Rutkevich A.V., Polyakov E.A., Sysoev I.Y. NAND Flash memory controller IP-core // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2014. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2014. Part 4. P. 7-12.
URL of paper

Copyright © 2009-2019 IPPM RAS. All Rights Reserved.

Design of site: IPPM RAS