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Probabilistic methods for reliability evaluation of combinational circuits  

Authors
 Stempkovsky A.L.
 Telpukhov D.V.
 Solovyev R.A.
 Telpukhova N.V.
Date of publication
 2016

Abstract
 Development of modern microelectronic devices is closely associated with the need to increase integration level, performance and reliability. With integration growth and size reduction, grows the importance of improving reliability and noise immunity of devices to different sources of interference and failure: technological faults, radiation, crosstalk, over time degradation, power surges, and others. This problem is especially acute in military, aerospace, medical and other fields of human activity associated with high risks to which undetected error may lead. At present, noise immunity becomes a prerequisite of efficiency and reliability of electronic equipment being developed. Therefore, research and development of methods aimed at improvement of microelectronic circuits fault tolerance are of high importance.
Despite the progress in the development of code protection methods used in storage, transfer and arithmetic processing of data, in order to provide the desired level of fault-tolerance of arithmetic and logic circuits, archaic methods of adding multiple redundancies are still used. Thus, it is important to develop efficient methods to increase noise immunity characteristics of logic circuits. The key aspect of this problem is the development of methods for estimation of the developed approaches efficiency.
The existing methods of fault tolerance analysis for combinational circuits require certain trade-off between complexity and accuracy because of the exponential computational complexity with primary inputs and number of elements in the case of accurate algorithms.
This paper contains a survey of different reliability estimation methods that are based on probabilistic properties of signals and gates. Two methods are presented and discussed: method based on probabilistic gate models (PGM) and single-pass method. Both the complexity and accuracy of each method is addressed and compared.
Study on computational complexity has demonstrated significant differences regarding the dependency on the number of inputs and the number of circuit elements, allowing one to develop some guidelines on the use of a particular method for a particular combinational circuit.
The accuracy of the methods was analyzed on a wide variety of schemes with different numbers reconvergent fan-outs. Both methods demonstrated the expected significant dependence on the reconvergence degree, while the accuracy of these methods was almost identical.
Further research will be devoted to the development of probabilistic methods of calculation of new fault-tolerance metrics, such as the logical sensitivity factor.
Keywords
 fault-tolerance, combinational circuits, logic masking, logic sensitivity factor.
Library reference
 Stempkovsky A.L., Telpukhov D.V., Solovyev R.A., Telpukhova N.V. Probabilistic methods for reliability evaluation of combinational circuits // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part 4. P. 121-126.
URL of paper
 http://www.mes-conference.ru/data/year2016/pdf/D017.pdf

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