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CMOS 65-nm static RAM on DICE cells with spacing groups of transistors  

 Stenin V.Ya.
 Katunin Yu.V.
 Stepanov P.V.
Date of publication

 The basis of static RAM with high immunity to single-event upsets is the DICE (Dual Interlocked Storage Cell) cell [1]. In bulk CMOS technologies, the node proximities of DICE with traditional layout design led to loss advantages with respect to 6-T cells [2]–[4]. Increasing the spacing between sensitive nodes requires non-traditional methods of the topology design. The experimental studies of 28-nm CMOS DICE triggers with transistors situated along the straight line [4] demonstrated quite a low single event rate (SER) in all directions of the nuclear particle tracks except of the line layout position of cell transistors. The purpose of our work is to design new DICE layout.
The new specific DICE cell layout design bases on the spacing the two transistor groups of the DICE cell each of them consists of the two transistors column – the one opened pair N-PMOS transistors and the one closed pair N-PMOS transistors [5], [6]. We named the layout of this cell as Spaced Transistor Groups DICE - STG DICE.
The result of the single nuclear particle strike only on the one transistor group of the STG DICE is a single event transient (SET) but not a single-event upset (SEU). The single-event upset results from the strike on the both transistor groups. The second group may fail status of the STG DICE cell, if the impact on the second group of transistors exceeded a threshold value. The single-event upset depends upon the charge collection time of the first group tCOLL.GR1 and the upset delay or switching time delay of the second group of STG DICE tDEL.SW.GR2 [7].
It is believed that one group (first) has got its part of a charge instantly (correspondingly of the vicinity this group of transistors to a track of a particle), and the second group obtains a charge during the diffusion of charge carriers arising on this track. The real values of the collected charge do not exceed 1 pC and the charge collection time of the first group tCOLL.GR1 is less than 1 ns [8].
The threshold switching delay of the second group tDEL.SW.GR2.THR is approximated by the function:
tDEL.SW.GR2.THR = 0.01(100 µA/IĚ) 0.25(3+lg2) (ns),
IM is the amplitude of the node diffusion current pulse in µA. This formula is fit for DICE with the smallest transistor channel widths for the design rule. If the charge collection time of the first group tCOLL.GR1 is less than the threshold delay switching time of the second group tCOLL.GR1 < tDEL.SW.GR2.THR, upset does not occurs. The upset occurs if tCOLL.GR1 ≥ tDEL.SW.GR2 = f(QCOLL2, IM, τCOLL2). If the particle track is on the vicinity of both groups, the delay switching time is small so far as the critical charge amount is collected simultaneously at nodes of both groups. The more spacing the two transistor groups – the less a cell upset probability.
For increasing of the immunity to impact of a single nuclear particle, DICE cells was designed in the form of two Spaced Transistor Groups [5], [6], and [9]. DICE cells, in turn, were united in basic memory elements by alternating its transistor groups. The two groups are connected by two wires. Four cells of a STG DICE basic 65-nm memory element have only 8 connection wires. We have four STG DICE memory cells with the so large spacing of transistor groups and the small area which are impossible for the traditional layout of DICE cells.
The distances between sensitive pairs of reverse biased pn drain-substrate junctions of transistors, which are situated in one of two logical states of a cell, are denoted as DAC, DAD, DBD, DBC, and DAB. DAB is the distance between the NMOS and ĐMOS transistors of the one group whose joint fault does not result in a cell upset.
The STG DICE layout used in the static cache RAM [9] and multiport RAM [10] (the register file - RF). In the logic state of nodes ABCD = 0101, the first pair N- and PMOS transistors, namely, NDPA is in a closed state, and the both transistors of the second pair NAPB are open. In the same logic state of nodes ABCD = 0101, in the second group the pair of NBPC is in the closed state and the pair NCPD is open. After impact a single nuclear particle only to transistors of the one group, STG DICE trigger passes to a transient state from which the trigger returns to its original steady state without a failure after finishing of the charge collection time tCOLL.GR1 [7]. About design 28-nm STG DICE – in [9].
The layout of 65-nm CMOS multiport STG DICE memory cell contained the DICE trigger with two transistor groups, four write ports and eight read ports. Regions n+ and p+ around the PMOS and NMOS transistors are the regions of the ohm contacts at the boundaries of the P-substrate and N-well. The two-phase inverters [10] replaced the traditional CMOS inverters, used in multiport memory cells for the galvanic isolation of the trigger nodes from the nodes of read ports.
The cache RAM of 128×32 bits and the multiport RAM (the register file - RF) of 32×64 bit on STG DICE cells, the cache RAM of 128×32 bits, and the multiport RAM of 32×64 bit on 6-transistor (6-T) cells were fabricated on the common crystal of the microprocessor system.
The minimum space between the closed transistors of two transistor groups of one memory cell DMIN = 2.32 μm for the cache RAM of 128×32 bits and DMIN = 3.09 μm for the multiport RAM (the register file - RF) of 32×64 bit on the basis of STG DICE cells. The spacing of sensitive pairs of the transistors for each of the three two-phase inverters in multiport (RF) STG DICE is equal 3.09 μm so as the minimum node spacing of the DICE trigger for the multiport STG DICE cell.
The STG DICE cell upset by laser tests have been performed using back-side crystal irradiation of the microcircuit. The parameters of the laser test system [11] are the next. Wavelength is 1.064 μm; laser pulse duration is 70 ps; laser energy is 0.1–5.0 nJ; energy resolution is 0.05 nJ; laser spot size is 3.5 μm; step of a spot displacement is 3.0 μm. The noise immunity was characterized using pulse laser verification.
The maximum multiplicity of cache 6-T RAM (MCU) is 21. The multiport STG DICE RAM has no multiple cell upsets. The maximum multiplicity of multiport 6-T RAM (MCU) is 3. The multiport STG DICE RAM has no multiple cell upsets. Testing shows the dependence of maximum multiplicity of multi-cell upsets (MCU) versus the pulse laser energy. The laser spot pulse results in the “active” region with induced electron-hole pairs where cell upsets take place. The diameter of the “active” upset region is the function of the laser energy.
Using maps of deviations of upset cell centers relative to the laser spot centers for STG DICE RAM and deviations of upset cell centers relative to the laser spot centers for 6T RAM it is possible to compare the “active” regions with induced electron-hole pairs where cell upsets take place, and compare the noise immunity of variants of RAM’s. The diameters of the “active” upset cell areas for all STG DICE RAM’s and 6-T RAM’s are much the same (~10 μm) for 5 nJ laser pulse energy. It proves the reliable result that we have not upsets of STG DICE RAM to the threshold energy 3.5–4 nJ when corresponding diameters of “active” laser pulse areas are less 8.5 μm. The upset of STG DICE memory cell takes place only if the critical charges are collected simultaneously at all STG DICE cell nodes of both transistor groups with spacing 3–3.5 μm.
The new noise immune memory STG DICE layout design was used in reliable static cache RAM and multiport RAM (the register file). The new layout design hardened cell can be implemented in nanoscale CMOS.
 memory cell, RAM, noise immunity, layout, topology, single nuclear particle, laser verification
Library reference
 Stenin V.Ya., Katunin Yu.V., Stepanov P.V. CMOS 65-nm static RAM on DICE cells with spacing groups of transistors // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part 4. P. 127-132.
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