Authors Papers Year of conference Themes Organizations To MES conference
|Built-in self-repair for SRAM with redundant elements
| ||Shchigorev L.A.|
|Date of publication|
| ||Memory elements are the most dominating elements in the modern system-on-chips. Usually redundant elements are used for yield improvement after manufacturing testing. But if the existing redundancy was not used as the yield improvement factor, in the future it can be used for the replacement of the faulty elements. This article is devoted to the repair of static random access memory with redundant elements, more precisely, with redundant columns.|
Due to the application of the exhaustive search for CRV, 2-D redundancy (columns and rows) is not used because of the huge number of possible combinations. The table with the comparative analysis for maximum time of self-repair operations for different word width is also presented. 1-D column redundancy is applied due to its greater functional fault coverage.
The self-repair operation is preceded by the self-testing operation. The method of redundancy analysis depends on the way of the built-in self-test (BIST) units status information producing. The proposed built-in self-repair (BISR) scheme interacts with the BIST unit, which has only single-bit status signal. Therefore, the search of column repair vector (CRV) is executed by using the exhaustive search. Furthermore, it is suggested that the operation will be performed every time the system turns on or restarts, thatís why it is assumed that the data storage takes place in the volatile memory.
The considered memory block has two redundant columns Ė one column per each half of the word. Thatís why the maximum number of MBIST operation for N-bit per word memory block with different memory configuration is (N/2)2 + 1 (1 here means the first test operation without spare elements). For reducing the maximum number of test iterations, the word width dividing is provided.
For the investigation, the most popular word widths were selected: 8, 16, 32 and 64 bits. The simulation results show, that the maximum required number of clock cycles for self-repair operation of 64-bit information word which is divided into 8 words, each consisting of 8 bits, reduces in 60,28 times.
| ||memory repair, memory repair analyzer, self-test, system-on-chip (SoC), redundancy, spare elements, SRAM, memory reconfiguration, column repair vector (CRV).|
| ||Shchigorev L.A. Built-in self-repair for SRAM with redundant elements // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part 3. P. 178-185.|
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