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The logical elements of comparison for the sub-100 nm CMOS selectors of associative memory  

Authors
 Stenin V.Ya.
 Antonyuk A.V.
Date of publication
 2016

Abstract
 The basic comparison elements for registers-selectors of associative memory (or translation lookaside buffer – TLB) are combinational logic elements “Exclusive OR” and the memory cell, which typically is CMOS 6-transistor cell [1]. With decreasing technological rules to the CMOS 65 nm and below has decreased the reliability of the associative memory, executed according to such design rules, used in conditions of exposure to single nuclear particles.
Easy replacement of the 6-transistor cell in the memory cell with high resistance to single effects, which is a memory cell DICE (Dual Interlocked Storage Cell) [2], does not solve the problem of increasing the hardness of comparison elements for CMOS registers-selectors of associative memory units. Characteristic of nano-scale design rules, the reduction of distances between pairs of sensitive nodes in the traditional version of the DICE cells when scaling the topology of their DICE cell is accompanied by loss of its advantages in terms of hardness relative to a 6-transistor cell [3], [4]. Experimental studies [5] the new 65-nm CMOS memory cells STG DICE [6], [7] with the transistors spaced into two groups, showed their high noise resistance compared with 6-transistor memory cells.
The aim of this paper is to give an analysis of the logic comparison element compare to CMOS selectors associative memory units based on STG DICE memory cells that provide potentially high noise immunity of this logic comparison gate.
The element of comparison to CMOS selectors was created using Spaced Transistor Groups DICE (STG DICE) trigger. STG DICE trigger consists of two groups of transistors each group has the opened and closed pairs of N- and PMOS transistors [6], [7]. The combinational logic of the comparison element is on the logical element “Exclusive OR”, denoted as XOR.
We consider two variants of the scheme of logical element “Exclusive OR” (XOR). The first option is on two inverters with a third state; the second – on traditional inverters and pass gates on pairs of N - and PMOS transistors.
Write data to STG DICE is carried out in four nodes of the trigger A, B, C, D through the passed gates. When you write data to, the bit line serves the data written in the differential form - in normal form and in inverted. The active level on the sampling line opens gates recording data (first two variables) on the four nodes of the trigger A, B, C, D.
In compare mode (selection) of data on two intputs serves a sequences of signals in normal and inverse form. On the output of the element of the XOR is result from a comparison of the data. The logical element comparison has the function of the following form:
YOUT = XIN1∙XBD + XIN2∙XAC,
XAC = XA = XC – logic values of nodes A and C that have the same normal value in the stationary state of the trigger STG DICE; XBD = XB = XD – logic values of nodes B and D have the inverse value in the stationary state of the trigger. XIN1 – normal (direct) logic level at the Input 1 of the element; XIN2 = nXIN1 – inverted logic level of the signal at the Input 2 of the element; YOUT is the logical level at the output of the XOR element.
The impact of the particle on one of the groups trigger STG DICE does not cause a failure, and puts the trigger in a temporary unsteady state due to a transient (Single Event Transient – SET).
The fault (Single Event Upset – SEU) of trigger STG DICE depends on the duration of charge collection on the first group and at the same time from the delay time switching on of the second group of transistors of trigger STG DICE [8]. After exposure on the first group, if impact on the second group was small, the trigger returns to its original state. The value of charge which was collected to the first group just the same as that of the inverter [9], [10], no more 1 pC, and the time of its collection tCOLL.GR1 does not exceed 0.4–1 ns, which determines the duration of the effect of the impact when crashing.
To protect against the occurrence of latch-up during the impact of single nuclear particles were used n+ and p+ guard rings in the form of ohmic contacts at the boundaries of the areas of P-substrate and the N-wells. Using separated ohmic contacts distributed on P-substrate are used to increase the rate of pass the induced charge from the bulk of semiconductor to the power buses and ground buses.
The basic group of transistors contains one group of transistors of the trigger STG DICE, and the inverter with a third state (half part the transistors of a logic gate XOR). Two groups of transistors of the STG DICE trigger connected by two wires, which reduces costs by chip when separating the basic groups on the chip in comparison with the traditional topology DICE.
Schematics and topologies of basic transistors groups of the CMOS units were designed in CAD Sńhematic Cadence Virtuoso Editor and Cadence Virtuoso Layout Editor. Verification of the topology was carried out using CAD packages from Mentor Graphics: Calibre nmDRC and Calibre nmLVS.
The basic groups in the topology of the register-selector form a sequence in which two basic groups of the specific logical block is formed by several groups of other elements (four or eight, for example), which allows forming logic comparison elements with the large distances between mutually sensitive nodes of the two such groups of the each logic comparison element. This increases the noise immunity of the logical comparison elements because it significantly decreases the fraction of nuclear particles with large linear energy losses with the tracks in this very limited space of directions.
The parameters of comparison elements on design rule bulk CMOS 65-nm are the next. The width of NMOS and PMOS transistors are WN = 300 nm and WP = 360 nm; the height and the width of the basic group are HGR = 2.45 µm, and WGR = 2.4 μm; a leakage current on the output of XOR element is IOUT.LEAK = 30-33 pA; the propagation delay of the XOR is tDEL.PROP = 20-25 ps (CL = 3 fF). Distances between pairs of the mutually sensitive logical nodes of two groups of the comparison element for the CMOS 65-nm block of the four basic groups: LNA-NC = 4.55 µm, LPB-PD = 4.55 µm, LPB-NC = 4.15 µm, L NA-PD = 5.15 µm.
The parameters of comparison elements on design rule bulk CMOS 28-nm are the next. The width of NMOS and PMOS transistors are WN = 200 nm and WP = 240 nm; the height and the width of the basic group are HGR = 1.4 µm, and WGR = 1.2 μm; a leakage current on the output of XOR element is IOUT.LEAK = 15-17 pA; the propagation delay of the XOR is tDEL.PROP = 25 ps (CL = 3 fF). Distances between pairs of the mutually sensitive logical nodes of two groups of the comparison element for the CMOS 28-nm block of the eight basic groups: LNA-NC = 4.65 µm, LPB-PD = 4.65 µm, LPB-NC = 4.45 µm, L NA-PD = 4.95 µm.
The distances between the sensitive nodes in the comparison elements with design rules of the CMOS 65-nm and 28-nm are almost the same due to the corresponding spacing between the basic groups of transistors within blocks of four (CMOS 65-nm) and eight (CMOS 28-nm) groups of transistors.
The analysis of the perspective options of the logical comparison elements on the STG DICE trigger, which are for CMOS selectors, associative memory devices composed of fault-tolerant microprocessor systems, implemented according to design rules bulk CMOS 65-nm and 28-nm.
Keywords
 logical element, memory cell, associative memory, topology layout, single nuclear particle, noise immunity
Library reference
 Stenin V.Ya., Antonyuk A.V. The logical elements of comparison for the sub-100 nm CMOS selectors of associative memory // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part 4. P. 133-138.
URL of paper
 http://www.mes-conference.ru/data/year2016/pdf/D070.pdf

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