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Fault-tolerant systolic processor for digital signal processing in modular code  

Authors
 Kalmykov I.A.
 Kalmykov M.I.
 Stepanova E.P.
 Veligosha A.V.
 Borodenko V.
Date of publication
 2016

Abstract
 The goal of this work is to increase the fault tolerance of the position independent special purpose processor for digital signal processing (DSP) with a parallel-pipeline computing organization due to rearranging in the polynomial residue number Federal State Educational Institution of Higher Professional Education North-Caucasus Federal University system (PRNS).
Higher requirements to the technical and economic features of modern digital signal processing (DSP) systems, wider ranges of their application and a growing tendency to use parallel methods of their organization have made it necessary to apply models of digital signal processing with the parallel-pipeline computing organization. To further increase the speed of signal processing, the article suggests using modular parallel codes. It shows the implementation of the two-dimensional signal transformation using a systolic processor that functions in the polynomial residue number system (PRNS).
The independence of residue processing in computing lanes, the equal status of the PRNS operating and check bases provide the foundation for the special-purpose processor (SP) reconfiguration when a fault appears. However, the absence of algorithms for orthogonal bases recomputation makes it impossible to widely apply the reconfiguration in order to restore the SP PRNS working condition. That is why designing a method of orthogonal bases recomputation with the gradual degradation of the position-independent structure of SP PRNS is a relevant task.
Keywords
 polynomial residue number system, modular codes, fault tolerance, digital signal processing
Library reference
 Kalmykov I.A., Kalmykov M.I., Stepanova E.P., Veligosha A.V., Borodenko V. Fault-tolerant systolic processor for digital signal processing in modular code // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part 1. P. 242-248.
URL of paper
 http://www.mes-conference.ru/data/year2016/pdf/D075.pdf

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