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Placement of Logic Cells of Integrated Circuits with Simultaneous Consideration of Performance and Thermal Mode  

 Harutyunyan A.G.
Date of publication

 With the development of microelectronics technology and increasing of integration of ICs, there are a number of new challenges to their design, among which the dominant ones are to ensure performance and thermal reliability. From the point of view of performance, the interconnections become the dominant factor in determining the total delay of input-output paths of digital circuits and dozens of times are greater than the delays of logic cells. The increase of power consumption has led to high operating temperatures and large thermal gradient, which in turn leads to lower performance and leads to serious problems of thermal reliability.
Under these conditions, along with diagrammatic techniques to improve performance and decrease power consumption of designed ICs, the degree of influence of physical design phase on IC quality steadily increases. Since on one hand, the topological distribution of temperature on the IC crystal mainly depends on the outcome of placement of logic gates and on the other hand, placement has a significant effect on further routing, which in turn determines the parasitic parameters and delay of interconnects, the placement becomes key task in the cycle of the physical IC design.
Modern commercial EDA of Ics, as a rule, solve placement problem in two stages: the initial placement, based on the approximate fast algorithms, providing good conditions for the subsequent final placement and final placement based on iterative algorithms of improving the results of the initial placement on a particular parameter.
At the same time, meeting the design requirements for performance and thermal mode usually leads to the second stage of placement.
If it is considered that the number of iterations in the second stage and therefore the time for solving the problem largely depend from the results of initial placement, the importance of developing multiparameter methods for initial placement of IC elements, which together with electrical connectivity of elements are to be considered as performance and temperature conditions, becomes evident.
In this paper, an approach to the initial placement of digital IC elements that provide common account of the total length of interconnects, signal propagation delays in the circuit diagrams and topological uniformity of thermal field on the surface of the chip is proposed. The proposed approach is based on the use of multi-parameter placement criteria, the mathematical form of which is an additive function of private one-parameter criteria. To this end, private criteria of considering delays in interconnects and uniformity of distributing temperature on IC surface, are proposed, the mathematical form of which is identical to the traditional criterion of minimization of the total length of interconnects. This enables their joint representation in the form of an additive function and application of successive algorithms of initial placement.
A simple algorithm for sequential placement, based on adjacency matrix and the recursive repetition of the subsequent general procedures is implemented. A cell, having a minimum value of precedent function, defined as the difference between the connectivity of the next placed cell with not yet placed and already placed cells, is placed in recurrent position.
Testing of the method for placing cells of a number of text schemes showed high efficiency of controlling private quality indicators by variation of weighting coefficients. The proposed method can be implemented into existing EDA tools as a subsystem of initial placement of standard cells, and the results can serve as a start for further optimization of the placement.
 digital integrated circuit, initial placement, delay in the interconnections, uniform temperature distribution, multiparameter placement.
Library reference
 Harutyunyan A.G. Placement of Logic Cells of Integrated Circuits with Simultaneous Consideration of Performance and Thermal Mode // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part 3. P. 165-170.
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