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Organization of instruction pipeline in ELcore-õxTM DSP-cores of “MULTICORE” IP-library

Authors
 Belyaev A.A.
Date of publication
 2005

Abstract
 Organization of instruction pipeline in ELcore-õxTM DSP-cores is discussed. Data path structure and operation timing diagrams for different types of DSP-cores are considered.
Keywords
 IP-library, DSP-cores, processor performance, pipeline depth
Library reference
 Belyaev A.A. Organization of instruction pipeline in ELcore-õxTM DSP-cores of “MULTICORE” IP-library // Problems of Perspective Microelectronic Systems Development - 2005. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2005. P. 508-515.
URL of paper
 http://www.mes-conference.ru/data/year2005/76.doc

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