Home         Authors   Papers   Year of conference   Themes   Organizations        To MES conference

System level design of the DSP processor IP-core with NeuroMatrix architecture  

 Dementev V.V.
Date of publication

 Program (behavioral) models are a popular tool for exploration design space of system on chip, and software development. There is a large gap between the speed and accuracy of the functional instruction set simulators and cycle-accurate models. Presence of processor cores causes necessity to maintain the parallel development of software and hardware and to conduct a joint verification and debugging using one common behavioral model. The increasing complexity of VLSI and embedded software requires simulation technology which has modeling speed higher than RTL can give and sufficient accuracy for assessment of system performance. The degree of detail of a model is determined by the level of abstraction at which model is applied and its intended purpose. The report discusses usage of program models at the system design level (ESL) of processor IP-cores with NeuroMatrix architecture that are designed for digital processing (DSP). The aim of this work is to develop a model of the pipeline execution of commands with the level of structure detail such as processor-memory-switch that allows: debug software, evaluate the performance, explore design space and be reused. More accurate models of pipelined execution of commands are developed based on the functional model (ISS), which improved to the required precision through the implementation of the algorithm of the pipeline working in C ++ and support of interfaces in SystemC to ensure correct duration of exchange operations. Sufficient data for model development are extracted from RTL level. The accuracy of the program model should be sufficient for real-time task.
 instruction set simulator, cycle-accurate model, pipeline.
Library reference
 Dementev V.V. System level design of the DSP processor IP-core with NeuroMatrix architecture // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part 2. P. 225-232.
URL of paper

Copyright © 2009-2019 IPPM RAS. All Rights Reserved.

Design of site: IPPM RAS